Lines Matching refs:UARTREG
41 #define UARTREG(base, reg) (*REG32((base) + (reg))) macro
65 UARTREG(uart_base, UART_IMSC) &= ~(1 << 5); in pl011_mask_tx()
69 UARTREG(uart_base, UART_IMSC) |= (1 << 5); in pl011_unmask_tx()
74 uint32_t isr = UARTREG(uart_base, UART_TMIS); in pl011_uart_irq()
78 while ((UARTREG(uart_base, UART_FR) & (1 << 4)) == 0) { in pl011_uart_irq()
81 UARTREG(uart_base, UART_IMSC) &= ~((1 << 4) | (1 << 6)); // !rxim in pl011_uart_irq()
85 char c = static_cast<char>(UARTREG(uart_base, UART_DR)); in pl011_uart_irq()
112 UARTREG(uart_base, UART_ICR) = 0x3ff; in pl011_uart_init()
115 UARTREG(uart_base, UART_IFLS) = 0; // 1/8 rxfifo, 1/8 txfifo in pl011_uart_init()
118 UARTREG(uart_base, UART_IMSC) = (1 << 4) | // rxim in pl011_uart_init()
122 UARTREG(uart_base, UART_CR) |= (1 << 9); // rxen in pl011_uart_init()
139 UARTREG(uart_base, UART_IMSC) |= ((1 << 4) | (1 << 6)); // rxim in pl011_uart_getc()
149 while (UARTREG(uart_base, UART_FR) & (1 << 5)) in pl011_uart_pputc()
151 UARTREG(uart_base, UART_DR) = c; in pl011_uart_pputc()
157 if ((UARTREG(uart_base, UART_FR) & (1 << 4)) == 0) { in pl011_uart_pgetc()
158 return UARTREG(uart_base, UART_DR); in pl011_uart_pgetc()
175 while (UARTREG(uart_base, UART_FR) & (1 << 5)) { in pl011_dputs()
189 UARTREG(uart_base, UART_DR) = '\r'; in pl011_dputs()
192 UARTREG(uart_base, UART_DR) = *str++; in pl011_dputs()
220 UARTREG(uart_base, UART_CR) = (1 << 8) | (1 << 0); // tx_enable, uarten in pl011_uart_init_early()