Lines Matching refs:bit
26 const uint8_t bit; member
34 [board_mt8167::kClkThermal] = {.regs = kClkGatingCtrl1, .bit = 1},
35 [board_mt8167::kClkI2c0] = {.regs = kClkGatingCtrl1, .bit = 3},
36 [board_mt8167::kClkI2c1] = {.regs = kClkGatingCtrl1, .bit = 4},
37 [board_mt8167::kClkI2c2] = {.regs = kClkGatingCtrl1, .bit = 16},
38 [board_mt8167::kClkPmicWrapAp] = {.regs = kClkGatingCtrl1, .bit = 20},
39 [board_mt8167::kClkPmicWrap26M] = {.regs = kClkGatingCtrl1, .bit = 29},
40 [board_mt8167::kClkAuxAdc] = {.regs = kClkGatingCtrl1, .bit = 30},
41 [board_mt8167::kClkSlowMfg] = {.regs = kClkGatingCtrl8, .bit = 7},
42 [board_mt8167::kClkAxiMfg] = {.regs = kClkGatingCtrl8, .bit = 6},
43 [board_mt8167::kClkMfgMm] = {.regs = kClkGatingCtrl0, .bit = 2},
153 mmio_.Write32(1 << gate.bit, gate.regs.clr); in ClkEnable()
163 mmio_.Write32(1 << gate.bit, gate.regs.set); in ClkDisable()