aml-dsi-host.cpp - OpenGrok cross reference for /system/dev/display/astro-display/aml-dsi-host.cpp

Lines Matching refs:WRITE32_REG
22     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_IF_CFG, PHY_IF_CFG_STOP_WAIT_TIME |  in HostModeInit()
26     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_VCID, MIPI_DSI_VIRTUAL_CHAN_ID);  in HostModeInit()
29     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_COLOR_CODING, DPI_COLOR_CODING(SUPPORTED_DPI_FORMAT));  in HostModeInit()
40     WRITE32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL, 0);  in HostModeInit()
44         WRITE32_REG(MIPI_DSI, DW_DSI_VID_MODE_CFG,VID_MODE_CFG_LP_EN_ALL |  in HostModeInit()
48         WRITE32_REG(MIPI_DSI, DW_DSI_DPI_LP_CMD_TIM, LP_CMD_TIM_OUTVACT(LPCMD_PKT_SIZE) |  in HostModeInit()
52         WRITE32_REG(MIPI_DSI, DW_DSI_VID_PKT_SIZE, disp_setting.h_active);  in HostModeInit()
54         WRITE32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS, 0);  in HostModeInit()
55         WRITE32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE, 0);  in HostModeInit()
58         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HLINE_TIME, disp_setting.h_period);  in HostModeInit()
59         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HSA_TIME, disp_setting.hsync_width);  in HostModeInit()
60         WRITE32_REG(MIPI_DSI, DW_DSI_VID_HBP_TIME, disp_setting.hsync_bp);  in HostModeInit()
61         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VSA_LINES, disp_setting.vsync_width);  in HostModeInit()
62         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VBP_LINES, disp_setting.vsync_bp);  in HostModeInit()
63         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VACTIVE_LINES, disp_setting.v_active);  in HostModeInit()
64         WRITE32_REG(MIPI_DSI, DW_DSI_VID_VFP_LINES, (disp_setting.v_period -  in HostModeInit()
70     WRITE32_REG(MIPI_DSI, DW_DSI_CLKMGR_CFG,  in HostModeInit()
75     WRITE32_REG(MIPI_DSI, DW_DSI_MODE_CFG, opp);  in HostModeInit()
78     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_LPCLK_CFG,  in HostModeInit()
81     WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_CFG,  in HostModeInit()
89     WRITE32_REG(HHI, HHI_MIPI_CNTL0, MIPI_CNTL0_CMN_REF_GEN_CTRL(0x29) |  in PhyEnable()
95     WRITE32_REG(HHI, HHI_MIPI_CNTL1, MIPI_CNTL1_DSI_VBG_EN | MIPI_CNTL1_CTL);  in PhyEnable()
96     WRITE32_REG(HHI, HHI_MIPI_CNTL2, MIPI_CNTL2_DEFAULT_VAL); // 4 lane  in PhyEnable()
100     WRITE32_REG(HHI, HHI_MIPI_CNTL0, 0);  in PhyDisable()
101     WRITE32_REG(HHI, HHI_MIPI_CNTL1, 0);  in PhyDisable()
102     WRITE32_REG(HHI, HHI_MIPI_CNTL2, 0);  in PhyDisable()
166     WRITE32_REG(MIPI_DSI, MIPI_DSI_TOP_MEM_PD, 0);  in HostOn()
170     WRITE32_REG(MIPI_DSI, DW_DSI_CMD_MODE_CFG,CMD_MODE_CFG_CMD_LP_ALL);  in HostOn()
173     WRITE32_REG(MIPI_DSI, DW_DSI_PCKHDL_CFG, PCKHDL_CFG_EN_CRC_ECC);  in HostOn()