Lines Matching refs:WRITE32_REG
133 WRITE32_REG(DSI_PHY, MIPI_DSI_PHY_CTRL, PHY_CTRL_TXDDRCLK_EN | in PhyInit()
141 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM, in PhyInit()
146 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM1, dsi_phy_cfg_.clk_pre); in PhyInit()
148 WRITE32_REG(DSI_PHY, MIPI_DSI_HS_TIM, in PhyInit()
153 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_TIM, in PhyInit()
157 WRITE32_REG(DSI_PHY, MIPI_DSI_ANA_UP_TIM, ANA_UP_TIME); in PhyInit()
158 WRITE32_REG(DSI_PHY, MIPI_DSI_INIT_TIM, dsi_phy_cfg_.init); in PhyInit()
159 WRITE32_REG(DSI_PHY, MIPI_DSI_WAKEUP_TIM, dsi_phy_cfg_.wakeup); in PhyInit()
160 WRITE32_REG(DSI_PHY, MIPI_DSI_LPOK_TIM, LPOK_TIME); in PhyInit()
161 WRITE32_REG(DSI_PHY, MIPI_DSI_ULPS_CHECK, ULPS_CHECK_TIME); in PhyInit()
162 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_WCHDOG, LP_WCHDOG_TIME); in PhyInit()
163 WRITE32_REG(DSI_PHY, MIPI_DSI_TURN_WCHDOG, TURN_WCHDOG_TIME); in PhyInit()
165 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0); in PhyInit()
204 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_RST); in Shutdown()
205 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0x1f); in Shutdown()
218 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_ON); in Startup()
224 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL1, 0x00010044); in Startup()
225 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2); in Startup()
226 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x0); in Startup()
227 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL1, 0x00000074); in Startup()
228 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2); in Startup()
229 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x0); in Startup()
232 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_RSTZ, PHY_RSTZ_PWR_UP); in Startup()
248 WRITE32_REG(MIPI_DSI, DW_DSI_LPCLK_CTRL, (0x1 << LPCLK_CTRL_AUTOCLKLANE_CTRL) | in Startup()