Lines Matching refs:SET_BIT32
57 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL3, 1, 31, 1); in PllLockWait()
151 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1); in Disable()
152 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, 0, 5); in Disable()
153 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); in Disable()
156 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_EN_HPLL_G12A, 1); in Disable()
194 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1); in Enable()
197 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1); in Enable()
207 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); in Enable()
211 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 19, 1); in Enable()
212 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 15, 1); in Enable()
214 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 18, 1); // Undocumented register bit in Enable()
217 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 19, 1); // Undocumented register bit in Enable()
220 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 0, 21, 3); in Enable()
221 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 0, 12, 7); in Enable()
222 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 1, 20, 1); in Enable()
225 SET_BIT32(HHI, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 12, 3); in Enable()
227 SET_BIT32(HHI, HHI_MIPIDSI_PHY_CLK_CNTL, 1, 8, 1); in Enable()
229 SET_BIT32(HHI, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 0, 7); in Enable()
232 SET_BIT32(HHI, HHI_VIID_CLK_DIV, (d.clock_factor-1), VCLK2_XD, 8); in Enable()
236 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3); in Enable()
237 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1); in Enable()
241 SET_BIT32(HHI, HHI_VIID_CLK_DIV, 8, ENCL_CLK_SEL, 4); in Enable()
243 SET_BIT32(HHI, HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2); in Enable()
246 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1); in Enable()
247 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1); in Enable()
249 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1); in Enable()
253 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, ENCL_GATE_VCLK, 1); in Enable()