Lines Matching refs:WRITE32_REG
59 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL6, 0x55540000); // more magic in PllLockWait()
149 WRITE32_REG(VPU, ENCL_VIDEO_EN, 0); in Disable()
183 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL0, regVal); in Enable()
185 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL1, pll_cfg->pll_frac); in Enable()
186 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL2, 0x00); in Enable()
188 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL3, useFrac? 0x6a285c00 : 0x48681c00); in Enable()
189 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL4, useFrac? 0x65771290 : 0x33771290); in Enable()
190 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL5, 0x39272000); in Enable()
191 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL6, useFrac? 0x56540000 : 0x56540000); in Enable()
257 WRITE32_REG(VPU, ENCL_VIDEO_EN, 0); in Enable()
260 WRITE32_REG(VPU, VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2)); //TODO(payamm): macros in Enable()
263 WRITE32_REG(VPU, ENCL_VIDEO_MODE, 0x8000); // bit[15] shadown en in Enable()
264 WRITE32_REG(VPU, ENCL_VIDEO_MODE_ADV, 0x0418); // Sampling rate: 1 in Enable()
267 WRITE32_REG(VPU, ENCL_VIDEO_FILT_CTRL, 0x1000); in Enable()
268 WRITE32_REG(VPU, ENCL_VIDEO_MAX_PXCNT, d.h_period - 1); in Enable()
269 WRITE32_REG(VPU, ENCL_VIDEO_MAX_LNCNT, d.v_period - 1); in Enable()
270 WRITE32_REG(VPU, ENCL_VIDEO_HAVON_BEGIN, lcd_timing_.vid_pixel_on); in Enable()
271 WRITE32_REG(VPU, ENCL_VIDEO_HAVON_END, d.h_active - 1 + lcd_timing_.vid_pixel_on); in Enable()
272 WRITE32_REG(VPU, ENCL_VIDEO_VAVON_BLINE, lcd_timing_.vid_line_on); in Enable()
273 WRITE32_REG(VPU, ENCL_VIDEO_VAVON_ELINE, d.v_active - 1 + lcd_timing_.vid_line_on); in Enable()
274 WRITE32_REG(VPU, ENCL_VIDEO_HSO_BEGIN, lcd_timing_.hs_hs_addr); in Enable()
275 WRITE32_REG(VPU, ENCL_VIDEO_HSO_END, lcd_timing_.hs_he_addr); in Enable()
276 WRITE32_REG(VPU, ENCL_VIDEO_VSO_BEGIN, lcd_timing_.vs_hs_addr); in Enable()
277 WRITE32_REG(VPU, ENCL_VIDEO_VSO_END, lcd_timing_.vs_he_addr); in Enable()
278 WRITE32_REG(VPU, ENCL_VIDEO_VSO_BLINE, lcd_timing_.vs_vs_addr); in Enable()
279 WRITE32_REG(VPU, ENCL_VIDEO_VSO_ELINE, lcd_timing_.vs_ve_addr); in Enable()
280 WRITE32_REG(VPU, ENCL_VIDEO_RGBIN_CTRL, 3); in Enable()
281 WRITE32_REG(VPU, ENCL_VIDEO_EN, 1); in Enable()
283 WRITE32_REG(VPU, L_RGB_BASE_ADDR, 0); in Enable()
284 WRITE32_REG(VPU, L_RGB_COEFF_ADDR, 0x400); in Enable()
285 WRITE32_REG(VPU, L_DITH_CNTL_ADDR, 0x400); in Enable()
288 WRITE32_REG(VPU, L_OEH_HS_ADDR, lcd_timing_.de_hs_addr); in Enable()
289 WRITE32_REG(VPU, L_OEH_HE_ADDR, lcd_timing_.de_he_addr); in Enable()
290 WRITE32_REG(VPU, L_OEH_VS_ADDR, lcd_timing_.de_vs_addr); in Enable()
291 WRITE32_REG(VPU, L_OEH_VE_ADDR, lcd_timing_.de_ve_addr); in Enable()
293 WRITE32_REG(VPU, L_OEV1_HS_ADDR, lcd_timing_.de_hs_addr); in Enable()
294 WRITE32_REG(VPU, L_OEV1_HE_ADDR, lcd_timing_.de_he_addr); in Enable()
295 WRITE32_REG(VPU, L_OEV1_VS_ADDR, lcd_timing_.de_vs_addr); in Enable()
296 WRITE32_REG(VPU, L_OEV1_VE_ADDR, lcd_timing_.de_ve_addr); in Enable()
300 WRITE32_REG(VPU, L_STH1_HS_ADDR, lcd_timing_.hs_he_addr); in Enable()
301 WRITE32_REG(VPU, L_STH1_HE_ADDR, lcd_timing_.hs_hs_addr); in Enable()
303 WRITE32_REG(VPU, L_STH1_HS_ADDR, lcd_timing_.hs_hs_addr); in Enable()
304 WRITE32_REG(VPU, L_STH1_HE_ADDR, lcd_timing_.hs_he_addr); in Enable()
306 WRITE32_REG(VPU, L_STH1_VS_ADDR, lcd_timing_.hs_vs_addr); in Enable()
307 WRITE32_REG(VPU, L_STH1_VE_ADDR, lcd_timing_.hs_ve_addr); in Enable()
310 WRITE32_REG(VPU, L_STV1_HS_ADDR, lcd_timing_.vs_hs_addr); in Enable()
311 WRITE32_REG(VPU, L_STV1_HE_ADDR, lcd_timing_.vs_he_addr); in Enable()
313 WRITE32_REG(VPU, L_STV1_VS_ADDR, lcd_timing_.vs_ve_addr); in Enable()
314 WRITE32_REG(VPU, L_STV1_VE_ADDR, lcd_timing_.vs_vs_addr); in Enable()
316 WRITE32_REG(VPU, L_STV1_VS_ADDR, lcd_timing_.vs_vs_addr); in Enable()
317 WRITE32_REG(VPU, L_STV1_VE_ADDR, lcd_timing_.vs_ve_addr); in Enable()
321 WRITE32_REG(VPU, L_DE_HS_ADDR, lcd_timing_.de_hs_addr); in Enable()
322 WRITE32_REG(VPU, L_DE_HE_ADDR, lcd_timing_.de_he_addr); in Enable()
323 WRITE32_REG(VPU, L_DE_VS_ADDR, lcd_timing_.de_vs_addr); in Enable()
324 WRITE32_REG(VPU, L_DE_VE_ADDR, lcd_timing_.de_ve_addr); in Enable()
327 WRITE32_REG(VPU, L_HSYNC_HS_ADDR, lcd_timing_.hs_hs_addr); in Enable()
328 WRITE32_REG(VPU, L_HSYNC_HE_ADDR, lcd_timing_.hs_he_addr); in Enable()
329 WRITE32_REG(VPU, L_HSYNC_VS_ADDR, lcd_timing_.hs_vs_addr); in Enable()
330 WRITE32_REG(VPU, L_HSYNC_VE_ADDR, lcd_timing_.hs_ve_addr); in Enable()
333 WRITE32_REG(VPU, L_VSYNC_HS_ADDR, lcd_timing_.vs_hs_addr); in Enable()
334 WRITE32_REG(VPU, L_VSYNC_HE_ADDR, lcd_timing_.vs_he_addr); in Enable()
335 WRITE32_REG(VPU, L_VSYNC_VS_ADDR, lcd_timing_.vs_vs_addr); in Enable()
336 WRITE32_REG(VPU, L_VSYNC_VE_ADDR, lcd_timing_.vs_ve_addr); in Enable()
338 WRITE32_REG(VPU, L_INV_CNT_ADDR, 0); in Enable()
339 WRITE32_REG(VPU, L_TCON_MISC_SEL_ADDR, ((1 << kStv1Sel) | (1 << kStv2Sel))); in Enable()
341 WRITE32_REG(VPU, VPP_MISC, READ32_REG(VPU, VPP_MISC) & ~(VPP_OUT_SATURATE)); in Enable()