osd.cpp - OpenGrok cross reference for /system/dev/display/astro-display/osd.cpp

Lines Matching refs:WRITE32_REG
188     WRITE32_REG(VPU, VIU_OSD_BLEND_CTRL,  in DefaultSetup()
199     WRITE32_REG(VPU, OSD1_BLEND_SRC_CTRL,  in DefaultSetup()
206     WRITE32_REG(VPU, OSD2_BLEND_SRC_CTRL,  in DefaultSetup()
214     WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_DATA0,  in DefaultSetup()
219     WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_ALPHA,  in DefaultSetup()
225     WRITE32_REG(VPU,  in DefaultSetup()
229     WRITE32_REG(VPU,  in DefaultSetup()
233     WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND0_SIZE,  in DefaultSetup()
236     WRITE32_REG(VPU, VIU_OSD_BLEND_BLEND1_SIZE,  in DefaultSetup()
241     WRITE32_REG(VPU, VPP_OSD1_IN_SIZE,  in DefaultSetup()
245     WRITE32_REG(VPU, VPP_OSD1_BLD_H_SCOPE,  in DefaultSetup()
247     WRITE32_REG(VPU, VPP_OSD1_BLD_V_SCOPE,  in DefaultSetup()
252     WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W3 , data32);  in DefaultSetup()
254     WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W4, data32);  in DefaultSetup()
256     WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W1, ((fb_width_ - 1) & 0x1fff) << 16);  in DefaultSetup()
257     WRITE32_REG(VPU, VPU_VIU_OSD1_BLK0_CFG_W2, ((fb_height_ - 1) & 0x1fff) << 16);  in DefaultSetup()
290         WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, data32);  in EnableScaling()
293         WRITE32_REG(VPU, VPU_VPP_OSD_SC_CTRL0, 0);  in EnableScaling()
306         WRITE32_REG(VPU, VPU_VPP_OSD_SCI_WH_M1, data32);  in EnableScaling()
308         WRITE32_REG(VPU, VPU_VPP_OSD_SCO_H_START_END, data32);  in EnableScaling()
310         WRITE32_REG(VPU, VPU_VPP_OSD_SCO_V_START_END, data32);  in EnableScaling()
319     WRITE32_REG(VPU, VPU_VPP_OSD_VSC_CTRL0, data32);  in EnableScaling()
327     WRITE32_REG(VPU, VPU_VPP_OSD_HSC_CTRL0, data32);  in EnableScaling()
336         WRITE32_REG(VPU, VPU_VPP_OSD_VSC_INI_PHASE, data32);  in EnableScaling()
438     WRITE32_REG(VPU, VPP_POSTBLEND_H_SIZE, display_width_);  in HwInit()
444     WRITE32_REG(VPU, VPP_OFIFO_SIZE, regVal);  in HwInit()
454     WRITE32_REG(VPU, VPU_VIU_OSD1_FIFO_CTRL_STAT, regVal);  in HwInit()
455     WRITE32_REG(VPU, VPU_VIU_OSD2_FIFO_CTRL_STAT, regVal);  in HwInit()
463     WRITE32_REG(VPU, VPU_VIU_OSD1_CTRL_STAT , regVal);  in HwInit()
464     WRITE32_REG(VPU, VPU_VIU_OSD2_CTRL_STAT , regVal);  in HwInit()
473         WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]);  in HwInit()
478         WRITE32_REG(VPU, VPU_VPP_OSD_SCALE_COEF, osd_filter_coefs_bicubic[i]);  in HwInit()
482     WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_H_SCOPE, display_width_ - 1);  in HwInit()
483     WRITE32_REG(VPU, VPU_VPP_OSD1_BLD_V_SCOPE, display_height_ - 1);  in HwInit()
484     WRITE32_REG(VPU, VPU_VPP_OUT_H_V_SIZE, display_width_ << 16 | display_height_);  in HwInit()