Lines Matching refs:SET_BIT32
118 SET_BIT32(VPU, VPP_OFIFO_SIZE, 0xFFF, 0, 12); in VppInit()
121 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0x7, 12, 3); in VppInit()
145 SET_BIT32(VPU, VPP_WRAP_OSD1_MATRIX_EN_CTRL, 1, 0, 1); in VppInit()
166 SET_BIT32(VPU, VPP_WRAP_OSD2_MATRIX_EN_CTRL, 1, 0, 1); in VppInit()
187 SET_BIT32(VPU, VPP_WRAP_OSD3_MATRIX_EN_CTRL, 1, 0, 1); in VppInit()
213 SET_BIT32(VPU, VPP_POST2_MATRIX_EN_CTRL, 1, 0, 1); in VppInit()
216 SET_BIT32(VPU, VPP_MATRIX_CTRL, 1, 0, 1); in VppInit()
217 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0, 8, 3); in VppInit()
234 SET_BIT32(VPU, VPP_MATRIX_CLIP, 0, 5, 3); in VppInit()
241 SET_BIT32(HHI, HHI_VPU_CLK_CNTL, 1, 8, 1); in ConfigureClock()
251 SET_BIT32(HHI, HHI_VAPBCLK_CNTL, 1, 8, 1); in ConfigureClock()
253 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 0, 0, 8); in ConfigureClock()
264 SET_BIT32(AOBUS, AOBUS_GEN_PWR_SLEEP0, 0, 8, 1); // [8] power on in PowerOn()
268 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG0, 0, i, 2); in PowerOn()
272 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG1, 0, i, 2); in PowerOn()
275 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0, 0, 2); in PowerOn()
278 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0, i, 2); in PowerOn()
281 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0, 30, 2); in PowerOn()
285 SET_BIT32(HHI, HHI_MEM_PD_REG0, 0, i, 1); in PowerOn()
301 SET_BIT32(AOBUS, AOBUS_GEN_PWR_SLEEP0, 0, 9, 1); // [9] VPU_HDMI in PowerOn()
318 SET_BIT32(AOBUS, AOBUS_GEN_PWR_SLEEP0, 1, 9, 1); // ISO in PowerOff()
323 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG0, 0x3, i, 2); in PowerOff()
327 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG1, 0x3, i, 2); in PowerOff()
330 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2); in PowerOff()
333 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0x3, i, 2); in PowerOff()
336 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2); in PowerOff()
340 SET_BIT32(HHI, HHI_MEM_PD_REG0, 0x1, i, 1); in PowerOff()
346 SET_BIT32(AOBUS, AOBUS_GEN_PWR_SLEEP0, 1, 8, 1); // PDN in PowerOff()
348 SET_BIT32(HHI, HHI_VAPBCLK_CNTL, 0, 8, 1); in PowerOff()
349 SET_BIT32(HHI, HHI_VPU_CLK_CNTL, 0, 8, 1); in PowerOff()