Lines Matching refs:WRITE32_REG
119 WRITE32_REG(VPU, VPP_HOLD_LINES, 0x08080808); in VppInit()
127 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1, in VppInit()
129 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2, in VppInit()
131 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF00_01, in VppInit()
133 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF02_10, in VppInit()
135 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF11_12, in VppInit()
137 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF20_21, in VppInit()
139 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF22, in VppInit()
141 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_OFFSET0_1, in VppInit()
143 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_OFFSET2, in VppInit()
148 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1, in VppInit()
150 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2, in VppInit()
152 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF00_01, in VppInit()
154 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF02_10, in VppInit()
156 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF11_12, in VppInit()
158 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF20_21, in VppInit()
160 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_COEF22, in VppInit()
162 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_OFFSET0_1, in VppInit()
164 WRITE32_REG(VPU, VPP_WRAP_OSD2_MATRIX_OFFSET2, in VppInit()
169 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1, in VppInit()
171 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2, in VppInit()
173 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF00_01, in VppInit()
175 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF02_10, in VppInit()
177 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF11_12, in VppInit()
179 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF20_21, in VppInit()
181 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_COEF22, in VppInit()
183 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_OFFSET0_1, in VppInit()
185 WRITE32_REG(VPU, VPP_WRAP_OSD3_MATRIX_OFFSET2, in VppInit()
189 WRITE32_REG(VPU, DOLBY_PATH_CTRL, 0xf); in VppInit()
195 WRITE32_REG(VPU, VPP_POST2_MATRIX_PRE_OFFSET0_1, in VppInit()
197 WRITE32_REG(VPU, VPP_POST2_MATRIX_PRE_OFFSET2, in VppInit()
199 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF00_01, in VppInit()
201 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF02_10, in VppInit()
203 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF11_12, in VppInit()
205 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF20_21, in VppInit()
207 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF22, in VppInit()
209 WRITE32_REG(VPU, VPP_POST2_MATRIX_OFFSET0_1, in VppInit()
211 WRITE32_REG(VPU, VPP_POST2_MATRIX_OFFSET2, in VppInit()
220 WRITE32_REG(VPU, VPP_MATRIX_PRE_OFFSET0_1, 0x0FC00E00); in VppInit()
221 WRITE32_REG(VPU, VPP_MATRIX_PRE_OFFSET2, 0x00000E00); in VppInit()
226 WRITE32_REG(VPU, VPP_MATRIX_COEF00_01, 0x04A80000); in VppInit()
227 WRITE32_REG(VPU, VPP_MATRIX_COEF02_10, 0x072C04A8); in VppInit()
228 WRITE32_REG(VPU, VPP_MATRIX_COEF11_12, 0x1F261DDD); in VppInit()
229 WRITE32_REG(VPU, VPP_MATRIX_COEF20_21, 0x04A80876); in VppInit()
230 WRITE32_REG(VPU, VPP_MATRIX_COEF22, 0x0); in VppInit()
231 WRITE32_REG(VPU, VPP_MATRIX_OFFSET0_1, 0x0); in VppInit()
232 WRITE32_REG(VPU, VPP_MATRIX_OFFSET2, 0x0); in VppInit()
240 WRITE32_REG(HHI, HHI_VPU_CLK_CNTL, ((kVpuMux << 9) | (kVpuDiv << 0))); in ConfigureClock()
245 WRITE32_REG(HHI, HHI_VPU_CLKB_CNTL, ((1 << 8) | (1 << 0))); in ConfigureClock()
249 WRITE32_REG(HHI, HHI_VAPBCLK_CNTL, (1 << 30) | (0 << 9) | (1 << 0)); in ConfigureClock()
256 WRITE32_REG(VPU, VPU_RDARB_MODE_L1C1, 0x0); in ConfigureClock()
257 WRITE32_REG(VPU, VPU_RDARB_MODE_L1C2, 0x10000); in ConfigureClock()
258 WRITE32_REG(VPU, VPU_RDARB_MODE_L2C1, 0x900000); in ConfigureClock()
259 WRITE32_REG(VPU, VPU_WRARB_MODE_L2C1, 0x20000); in ConfigureClock()