Lines Matching refs:reg_adr
882 unsigned int reg_adr; in dump_regs() local
885 for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr ++) { in dump_regs()
886 ladr = (reg_adr << 2); in dump_regs()
891 for (reg_adr = 0x1b00; reg_adr < 0x1c00; reg_adr ++) { in dump_regs()
892 ladr = VPU_REG_ADDR(reg_adr); in dump_regs()
896 for (reg_adr = 0x1c01; reg_adr < 0x1d00; reg_adr ++) { in dump_regs()
897 ladr = VPU_REG_ADDR(reg_adr); in dump_regs()
901 for (reg_adr = 0x2700; reg_adr < 0x2780; reg_adr ++) { in dump_regs()
902 ladr = VPU_REG_ADDR(reg_adr); in dump_regs()
906 for (reg_adr = HDMITX_TOP_SW_RESET; reg_adr < HDMITX_TOP_STAT0 + 1; reg_adr ++) { in dump_regs()
907 reg_val = hdmitx_readreg(display, reg_adr); in dump_regs()
908 DISP_INFO("TOP[0x%x]: 0x%x\n", reg_adr, reg_val); in dump_regs()
910 for (reg_adr = HDMITX_DWC_DESIGN_ID; reg_adr < HDMITX_DWC_I2CM_SCDC_UPDATE1 + 1; reg_adr ++) { in dump_regs()
911 if ((reg_adr > HDMITX_DWC_HDCP_BSTATUS_0 -1) && (reg_adr < HDMITX_DWC_HDCPREG_BKSV0)) { in dump_regs()
914 reg_val = hdmitx_readreg(display, reg_adr); in dump_regs()
918 if ((reg_adr < HDMITX_DWC_A_HDCPCFG0) || (reg_adr > HDMITX_DWC_CEC_CTRL)) in dump_regs()
919 DISP_INFO("DWC[0x%x]: 0x%x\n", reg_adr, reg_val); in dump_regs()