Lines Matching refs:SET_BIT32
37 SET_BIT32(HHI, reg, 1, 1, 28); \
38 SET_BIT32(HHI, reg, 0, 1, 28); \
63 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, n, PLL_CNTL_M_BITS, PLL_CNTL_M_START); in configure_hpll_clk_out()
66 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL1, m, PLL_CNTL1_DIV_FRAC_BITS, PLL_CNTL1_DIV_FRAC_START); in configure_hpll_clk_out()
72 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x1, 1, 28); in configure_hpll_clk_out()
73 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x0, 1, 28); in configure_hpll_clk_out()
86 SET_BIT32(PRESET, PRESET0_REGISTER, 1, 1, 7); in configure_od3_div()
89 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 19); in configure_od3_div()
90 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
114 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 18); in configure_od3_div()
116 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 18); in configure_od3_div()
117 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 2, 16); in configure_od3_div()
118 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
119 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 14, 0); in configure_od3_div()
121 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, shift_sel, 2, 16); in configure_od3_div()
122 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 15); in configure_od3_div()
123 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, shift_val, 14, 0); in configure_od3_div()
124 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
127 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 19); in configure_od3_div()
134 SET_BIT32(VPU, VPU_VPU_VIU_VENC_MUX_CTRL, pll->viu_type, 2, (pll->viu_channel == 1) ? 0 : 2); in configure_pll()
135 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 3, 9); in configure_pll()
136 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 7, 0); in configure_pll()
137 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 1, 1, 8); in configure_pll()
141 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od1 >> 1), 2, 21); in configure_pll()
144 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od2 >> 1), 2, 23); in configure_pll()
147 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od3 >> 1), 2, 19); in configure_pll()
151 SET_BIT32(HHI, HHI_VID_CLK_CNTL, 0, 3, 16); // select vid_pll_clk in configure_pll()
152 SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->vid_clk_div == 0) ? 0 : (pll->vid_clk_div - 1), 8, 0); in configure_pll()
153 SET_BIT32(HHI, HHI_VID_CLK_CNTL, 7, 3, 0); in configure_pll()
155 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, (pll->hdmi_tx_pixel_div == 12) ? in configure_pll()
157 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 5); //enable gate in configure_pll()
161 SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->encp_div == 12) ? in configure_pll()
163 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 2); //enable gate in configure_pll()
164 SET_BIT32(HHI, HHI_VID_CLK_CNTL, 1, 1, 19); in configure_pll()
167 SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->encp_div == 12) ? in configure_pll()
169 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 0); //enable gate in configure_pll()
170 SET_BIT32(HHI, HHI_VID_CLK_CNTL, 1, 1, 19); in configure_pll()