Lines Matching refs:pll_dev
31 static zx_status_t s905d2_pll_init_regs(aml_pll_dev_t* pll_dev) { in s905d2_pll_init_regs() argument
32 aml_hiu_dev_t* device = pll_dev->hiu; in s905d2_pll_init_regs()
34 if (pll_dev->pll_num == HIFI_PLL) { in s905d2_pll_init_regs()
44 } else if (pll_dev->pll_num == SYS_PLL) { in s905d2_pll_init_regs()
54 } else if (pll_dev->pll_num == GP0_PLL) { in s905d2_pll_init_regs()
68 zx_status_t s905d2_pll_init(aml_hiu_dev_t* device, aml_pll_dev_t* pll_dev, hhi_plls_t pll_num) { in s905d2_pll_init() argument
70 ZX_DEBUG_ASSERT(pll_dev); in s905d2_pll_init()
72 pll_dev->hiu = device; in s905d2_pll_init()
74 pll_dev->rate_table = s905d2_pll_get_rate_table(pll_num); in s905d2_pll_init()
75 pll_dev->rate_idx = 0; in s905d2_pll_init()
76 pll_dev->frequency = 0; in s905d2_pll_init()
77 pll_dev->pll_num = pll_num; in s905d2_pll_init()
78 pll_dev->rate_count = s905d2_get_rate_table_count(pll_num); in s905d2_pll_init()
80 ZX_DEBUG_ASSERT(pll_dev->rate_table); in s905d2_pll_init()
81 ZX_DEBUG_ASSERT(pll_dev->rate_count); in s905d2_pll_init()
84 s905d2_pll_disable(pll_dev); in s905d2_pll_init()
86 return s905d2_pll_init_regs(pll_dev); in s905d2_pll_init()
89 bool s905d2_pll_disable(aml_pll_dev_t* pll_dev) { in s905d2_pll_disable() argument
90 uint32_t offs = hiu_get_pll_offs(pll_dev); in s905d2_pll_disable()
91 uint32_t ctl0 = hiu_clk_get_reg(pll_dev->hiu, offs); in s905d2_pll_disable()
96 hiu_clk_set_reg(pll_dev->hiu, offs, ctl0); in s905d2_pll_disable()
101 zx_status_t s905d2_pll_ena(aml_pll_dev_t* pll_dev) { in s905d2_pll_ena() argument
102 ZX_DEBUG_ASSERT(pll_dev); in s905d2_pll_ena()
104 uint32_t offs = hiu_get_pll_offs(pll_dev); in s905d2_pll_ena()
105 uint32_t reg_val = hiu_clk_get_reg(pll_dev->hiu, offs); in s905d2_pll_ena()
109 hiu_clk_set_reg(pll_dev->hiu, offs, reg_val); in s905d2_pll_ena()
114 hiu_clk_set_reg(pll_dev->hiu, offs, reg_val); in s905d2_pll_ena()
118 if (hiu_clk_get_reg(pll_dev->hiu, offs) & HHI_PLL_LOCK) { in s905d2_pll_ena()
133 zx_status_t s905d2_pll_set_rate(aml_pll_dev_t* pll_dev, uint64_t freq) { in s905d2_pll_set_rate() argument
134 ZX_DEBUG_ASSERT(pll_dev); in s905d2_pll_set_rate()
138 zx_status_t status = s905d2_pll_fetch_rate(pll_dev, freq, &pll_rate); in s905d2_pll_set_rate()
143 bool ena = s905d2_pll_disable(pll_dev); in s905d2_pll_set_rate()
146 s905d2_pll_init_regs(pll_dev); in s905d2_pll_set_rate()
148 uint32_t offs = hiu_get_pll_offs(pll_dev); in s905d2_pll_set_rate()
149 uint32_t ctl0 = hiu_clk_get_reg(pll_dev->hiu, offs); in s905d2_pll_set_rate()
160 hiu_clk_set_reg(pll_dev->hiu, offs, ctl0); in s905d2_pll_set_rate()
162 hiu_clk_set_reg(pll_dev->hiu, offs + 4, pll_rate->frac); in s905d2_pll_set_rate()
165 return s905d2_pll_ena(pll_dev); in s905d2_pll_set_rate()