1 // Copyright 2017 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #include <hwreg/bitfields.h> 8 #include <zircon/types.h> 9 10 // Global Core Control Register 11 class GCTL : public hwreg::RegisterBase<GCTL, uint32_t> { 12 public: 13 DEF_FIELD(31, 19, PWRDNSCALE); 14 DEF_BIT(18, MASTERFILTBYPASS); 15 DEF_BIT(17, BYPSSETADDR); 16 DEF_BIT(16, U2RSTECN); 17 DEF_FIELD(15, 14, FRMSCLDWN); 18 DEF_FIELD(13, 12, PRTCAPDIR); 19 DEF_BIT(11, CORESOFTRESET); 20 DEF_BIT(9, U1U2TimerScale); 21 DEF_BIT(8, DEBUGATTACH); 22 DEF_FIELD(7, 6, RAMCLKSEL); 23 DEF_FIELD(5, 4, SCALEDOWN); 24 DEF_BIT(3, DISSCRAMBLE); 25 DEF_BIT(2, U2EXIT_LFPS); 26 DEF_BIT(1, GblHibernationEn); 27 DEF_BIT(0, DSBLCLKGTNG); Get()28 static auto Get() { return hwreg::RegisterAddr<GCTL>(0xc110); } 29 30 static constexpr uint32_t PRTCAPDIR_HOST = 1; 31 static constexpr uint32_t PRTCAPDIR_DEVICE = 2; 32 static constexpr uint32_t PRTCAPDIR_OTG = 3; 33 }; 34 35 // Global Status Register 36 class GSTS : public hwreg::RegisterBase<GSTS, uint32_t> { 37 public: 38 DEF_FIELD(31, 20, CBELT); 39 DEF_BIT(11, SSIC_IP); 40 DEF_BIT(10, OTG_IP); 41 DEF_BIT(9, BC_IP); 42 DEF_BIT(8, ADP_IP); 43 DEF_BIT(7, Host_IP); 44 DEF_BIT(6, Device_IP); 45 DEF_BIT(5, CSRTimeout); 46 DEF_BIT(4, BUSERRADDRVLD); 47 DEF_FIELD(1, 0, CURMOD); Get()48 static auto Get() { return hwreg::RegisterAddr<GSTS>(0xc118); } 49 }; 50 51 // Global USB2 PHY Configuration Register 52 class GUSB2PHYCFG : public hwreg::RegisterBase<GUSB2PHYCFG, uint32_t> { 53 public: 54 DEF_BIT(31, PHYSOFTRST); 55 DEF_BIT(29, ULPI_LPM_WITH_OPMODE_CHK); 56 DEF_FIELD(28, 27, HSIC_CON_WIDTH_ADJ); 57 DEF_BIT(26, INV_SEL_HSIC); 58 DEF_FIELD(24, 22, LSTRD); 59 DEF_FIELD(21, 19, LSIPD); 60 DEF_BIT(18, ULPIEXTVBUSINDICATOR); 61 DEF_BIT(17, ULPIEXTVBUSDRV); 62 DEF_BIT(15, ULPIAUTORES); 63 DEF_FIELD(13, 10, USBTRDTIM); 64 DEF_BIT(9, XCVRDLY); 65 DEF_BIT(8, ENBLSLPM); 66 DEF_BIT(7, PHYSEL); 67 DEF_BIT(6, SUSPENDUSB20); 68 DEF_BIT(5, FSINTF); 69 DEF_BIT(4, ULPI_UTMI_Sel); 70 DEF_BIT(3, PHYIF); 71 DEF_FIELD(2, 0, TOutCal); Get(uint32_t index)72 static auto Get(uint32_t index) { return hwreg::RegisterAddr<GUSB2PHYCFG>(0xc118 + index * 0x4); } 73 }; 74 75 // Global USB 3.1 PIPE Control Register 76 class GUSB3PIPECTL : public hwreg::RegisterBase<GUSB3PIPECTL, uint32_t> { 77 public: 78 DEF_BIT(31, PHYSoftRst); 79 DEF_BIT(30, HstPrtCmpl); 80 DEF_BIT(28, DisRxDetP3); 81 DEF_BIT(27, Ux_exit_in_Px); 82 DEF_BIT(26, ping_enhancement_en); 83 DEF_BIT(25, u1u2exitfail_to_recov); 84 DEF_BIT(24, request_p1p2p3); 85 DEF_BIT(23, StartRxDetU3RxDet); 86 DEF_BIT(22, DisRxDetU3RxDet); 87 DEF_FIELD(21, 19, DelayP1P2P3); 88 DEF_BIT(18, DELAYP1TRANS); 89 DEF_BIT(17, SUSPENDENABLE); 90 DEF_FIELD(16, 15, DATWIDTH); 91 DEF_BIT(14, AbortRxDetInU2); 92 DEF_BIT(13, SkipRxDet); 93 DEF_BIT(12, LFPSP0Algn); 94 DEF_BIT(11, P3P2TranOK); 95 DEF_BIT(10, P3ExSigP2); 96 DEF_BIT(9, LFPSFILTER); 97 DEF_BIT(8, RX_DETECT_to_Polling_LFPS_Control); 98 DEF_BIT(7, SSICEn); 99 DEF_BIT(6, TX_SWING); 100 DEF_FIELD(5, 3, TX_MARGIN); 101 DEF_FIELD(2, 1, SS_TX_DE_EMPHASIS); 102 DEF_BIT(0, ELASTIC_BUFFER_MODE); Get(uint32_t index)103 static auto Get(uint32_t index) { return hwreg::RegisterAddr<GUSB3PIPECTL>(0xc2c0 + index * 0x4); } 104 }; 105 106 // Global Event Buffer Address Register 107 class GEVNTADR : public hwreg::RegisterBase<GEVNTADR, uint64_t> { 108 public: 109 DEF_FIELD(63, 0, EVNTADR); Get(uint32_t index)110 static auto Get(uint32_t index) { return hwreg::RegisterAddr<GEVNTADR>(0xc400 + index * 0x10); } 111 }; 112 113 // Global Event Buffer Size Register 114 class GEVNTSIZ : public hwreg::RegisterBase<GEVNTSIZ, uint32_t> { 115 public: 116 DEF_BIT(31, EVNTINTRPTMASK); 117 DEF_FIELD(15, 0, EVENTSIZ); Get(uint32_t index)118 static auto Get(uint32_t index) { return hwreg::RegisterAddr<GEVNTSIZ>(0xc408 + index * 0x10); } 119 }; 120 121 // Global Event Buffer Count Register 122 class GEVNTCOUNT : public hwreg::RegisterBase<GEVNTCOUNT, uint32_t> { 123 public: 124 DEF_BIT(31, EVNT_HANDLER_BUSY); 125 DEF_FIELD(15, 0, EVNTCOUNT); Get(uint32_t index)126 static auto Get(uint32_t index) { return hwreg::RegisterAddr<GEVNTCOUNT>(0xc40c + index * 0x10); } 127 }; 128 129 // Device Configuration Register 130 class DCFG : public hwreg::RegisterBase<DCFG, uint32_t> { 131 public: 132 DEF_BIT(24, StopOnDisconnect); 133 DEF_BIT(23, IgnStrmPP); 134 DEF_BIT(22, LPMCAP); 135 DEF_FIELD(21, 17, NUMP); 136 DEF_FIELD(16, 12, INTRNUM); 137 DEF_FIELD(9, 3, DEVADDR); 138 DEF_FIELD(2, 0, DEVSPD); Get()139 static auto Get() { return hwreg::RegisterAddr<DCFG>(0xc700); } 140 141 static constexpr uint32_t DEVSPD_HIGH = 0; 142 static constexpr uint32_t DEVSPD_FULL = 1; 143 static constexpr uint32_t DEVSPD_LOW = 2; 144 static constexpr uint32_t DEVSPD_SUPER = 4; 145 }; 146 147 // Device Control Register 148 class DCTL : public hwreg::RegisterBase<DCTL, uint32_t> { 149 public: 150 DEF_BIT(31, RUN_STOP); 151 DEF_BIT(30, CSFTRST); 152 DEF_FIELD(28, 24, HIRDTHRES); 153 DEF_FIELD(23, 20, LPM_NYET_thres); 154 DEF_BIT(19, KeepConnect); 155 DEF_BIT(18, L1HibernationEn); 156 DEF_BIT(17, CRS); 157 DEF_BIT(16, CSS); 158 DEF_BIT(12, INITU2ENA); 159 DEF_BIT(11, ACCEPTU2ENA); 160 DEF_BIT(10, INITU1ENA); 161 DEF_BIT(9, ACCEPTU1ENA); 162 DEF_FIELD(8, 5, ULSTCHNGREQ); 163 DEF_FIELD(4, 1, TSTCTL); Get()164 static auto Get() { return hwreg::RegisterAddr<DCTL>(0xc704); } 165 }; 166 167 // Device Event Enable Register 168 class DEVTEN : public hwreg::RegisterBase<DEVTEN, uint32_t> { 169 public: 170 DEF_BIT(15, LDMEVTEN); 171 DEF_BIT(14, L1WKUPEVTEN); 172 DEF_BIT(13, StopOnDisconnectEn); 173 DEF_BIT(12, VENDEVTSTRCVDEN); 174 DEF_BIT(9, ERRTICERREVTEN); 175 DEF_BIT(8, L1SUSPEN); 176 DEF_BIT(7, SOFTEVTEN); 177 DEF_BIT(6, U3L2L1SuspEn); 178 DEF_BIT(5, HibernationReqEvtEn); 179 DEF_BIT(4, WKUPEVTEN); 180 DEF_BIT(3, ULSTCNGEN); 181 DEF_BIT(2, CONNECTDONEEVTEN); 182 DEF_BIT(1, USBRSTEVTEN); 183 DEF_BIT(0, DISSCONNEVTEN); Get()184 static auto Get() { return hwreg::RegisterAddr<DEVTEN>(0xc708); } 185 }; 186 187 // Device Status Register 188 class DSTS : public hwreg::RegisterBase<DSTS, uint32_t> { 189 public: 190 DEF_BIT(29, DCNRD); 191 DEF_BIT(28, SRE); 192 DEF_BIT(25, RSS); 193 DEF_BIT(24, SSS); 194 DEF_BIT(23, COREIDLE); 195 DEF_BIT(22, DEVCTRLHLT); 196 DEF_FIELD(21, 18, USBLNKST); 197 DEF_BIT(17, RXFIFOEMPTY); 198 DEF_FIELD(16, 3, SOFFN); 199 DEF_FIELD(2, 0, CONNECTSPD); Get()200 static auto Get() { return hwreg::RegisterAddr<DSTS>(0xc70c); } 201 202 // Link state in SS node 203 static constexpr uint32_t USBLNKST_U0 = 0x0; 204 static constexpr uint32_t USBLNKST_U1 = 0x1; 205 static constexpr uint32_t USBLNKST_U2 = 0x2; 206 static constexpr uint32_t USBLNKST_U3 = 0x3; 207 static constexpr uint32_t USBLNKST_ESS_DIS = 0x4; 208 static constexpr uint32_t USBLNKST_RX_DET = 0x5; 209 static constexpr uint32_t USBLNKST_ESS_INACT = 0x6; 210 static constexpr uint32_t USBLNKST_POLL = 0x7; 211 static constexpr uint32_t USBLNKST_RECOV = 0x8; 212 static constexpr uint32_t USBLNKST_HRESET = 0x9; 213 static constexpr uint32_t USBLNKST_CMPLY = 0xa; 214 static constexpr uint32_t USBLNKST_LPBK = 0xb; 215 static constexpr uint32_t USBLNKST_RESUME_RESET = 0xf; 216 217 // Link state in HS/FS/LS node 218 static constexpr uint32_t USBLNKST_ON = 0x0; 219 static constexpr uint32_t USBLNKST_SLEEP = 0x2; 220 static constexpr uint32_t USBLNKST_SUSPEND = 0x3; 221 static constexpr uint32_t USBLNKST_DISCONNECTED = 0x4; 222 static constexpr uint32_t USBLNKST_EARLY_SUSPEND = 0x5; 223 static constexpr uint32_t USBLNKST_RESET = 0xe; 224 static constexpr uint32_t USBLNKST_RESUME = 0xf; 225 226 // Connection speed 227 static constexpr uint32_t CONNECTSPD_HIGH = 0; 228 static constexpr uint32_t CONNECTSPD_FULL = 1; 229 static constexpr uint32_t CONNECTSPD_SUPER = 4; 230 static constexpr uint32_t CONNECTSPD_ENHANCED_SUPER = 5; 231 }; 232 233 // Device Active USB Endpoint Enable Register 234 class DALEPENA : public hwreg::RegisterBase<DALEPENA, uint32_t> { 235 public: 236 DEF_FIELD(31, 0, USBACTEP); Get()237 static auto Get() { return hwreg::RegisterAddr<DALEPENA>(0xc720); } 238 EnableEp(uint32_t ep)239 DALEPENA& EnableEp(uint32_t ep) { 240 *reg_value_ptr() |= (1 << ep); 241 return *this; 242 } 243 DisableEp(uint32_t ep)244 DALEPENA& DisableEp(uint32_t ep) { 245 *reg_value_ptr() &= ~(1 << ep); 246 return *this; 247 } 248 }; 249 250 // Device Physical Endpoint-n Command Parameter 2 Register 251 class DEPCMDPAR2 : public hwreg::RegisterBase<DEPCMDPAR2, uint32_t> { 252 public: 253 DEF_FIELD(31, 0, PARAMETER); Get(uint32_t index)254 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCMDPAR2>(0xc800 + index * 0x10); } 255 }; 256 257 // Device Physical Endpoint-n Command Parameter 1 Register 258 class DEPCMDPAR1 : public hwreg::RegisterBase<DEPCMDPAR1, uint32_t> { 259 public: 260 DEF_FIELD(31, 0, PARAMETER); Get(uint32_t index)261 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCMDPAR1>(0xc804 + index * 0x10); } 262 }; 263 264 // Device Physical Endpoint-n Command Parameter 0 Register 265 class DEPCMDPAR0 : public hwreg::RegisterBase<DEPCMDPAR0, uint32_t> { 266 public: 267 DEF_FIELD(31, 0, PARAMETER); Get(uint32_t index)268 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCMDPAR0>(0xc808 + index * 0x10); } 269 }; 270 271 // Variant of DEPCMDPAR1 for the DEPCFG command 272 class DEPCFG_DEPCMDPAR1 : public hwreg::RegisterBase<DEPCFG_DEPCMDPAR1, uint32_t> { 273 public: 274 DEF_BIT(31, FIFO_BASED); 275 DEF_FIELD(29, 25, EP_NUMBER); 276 DEF_BIT(24, STREAM_CAPABLE); 277 DEF_FIELD(23, 16, INTERVAL); 278 DEF_BIT(15, EBC); // External Buffer Control 279 DEF_BIT(14, EBC_NO_WRITE_BACK); // Don't write back HWO bit to the TRB descriptor 280 DEF_BIT(13, STREAM_EVT_EN); 281 DEF_BIT(10, XFER_NOT_READY_EN); 282 DEF_BIT(9, XFER_IN_PROGRESS_EN); 283 DEF_BIT(8, XFER_COMPLETE_EN); 284 DEF_FIELD(4, 0, INTR_NUM); Get(uint32_t index)285 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCFG_DEPCMDPAR1>(0xc804 + index * 0x10); } 286 }; 287 288 // Variant of DEPCMDPAR0 for the DEPCFG command 289 class DEPCFG_DEPCMDPAR0 : public hwreg::RegisterBase<DEPCFG_DEPCMDPAR0, uint32_t> { 290 public: 291 DEF_FIELD(31, 30, ACTION); 292 DEF_FIELD(25, 22, BURST_SIZE); // subtract one 293 DEF_FIELD(21, 17, FIFO_NUM); 294 DEF_BIT(15, INTERNAL_RETRY); 295 DEF_FIELD(13, 3, MAX_PACKET_SIZE); 296 DEF_FIELD(2, 1, EP_TYPE); Get(uint32_t index)297 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCFG_DEPCMDPAR0>(0xc808 + index * 0x10); } 298 299 static constexpr uint32_t ACTION_INITIALIZE = 0; 300 static constexpr uint32_t ACTION_RESTORE = 1; 301 static constexpr uint32_t ACTION_MODIFY = 2; 302 }; 303 304 // Device Physical Endpoint-n Command Register 305 class DEPCMD : public hwreg::RegisterBase<DEPCMD, uint32_t> { 306 public: 307 DEF_FIELD(31, 16, COMMANDPARAM); 308 DEF_FIELD(15, 12, CMDSTATUS); 309 DEF_BIT(11, HIPRI_FORCERM); 310 DEF_BIT(10, CMDACT); 311 DEF_BIT(8, CMDIOC); 312 DEF_FIELD(3, 0, CMDTYP); Get(uint32_t index)313 static auto Get(uint32_t index) { return hwreg::RegisterAddr<DEPCMD>(0xc80c + index * 0x10); } 314 315 // Command Types 316 static constexpr uint32_t DEPCFG = 1; // Set Endpoint Configuration 317 static constexpr uint32_t DEPXFERCFG = 2; // Set Endpoint Transfer Resource Configuration 318 static constexpr uint32_t DEPGETSTATE = 3; // Get Endpoint State 319 static constexpr uint32_t DEPSSTALL = 4; // Set Stall 320 static constexpr uint32_t DEPCSTALL = 5; // Clear Stall 321 static constexpr uint32_t DEPSTRTXFER = 6; // Start Transfer 322 static constexpr uint32_t DEPUPDXFER = 7; // Update Transfer 323 static constexpr uint32_t DEPENDXFER = 8; // End Transfer 324 static constexpr uint32_t DEPSTARTCFG = 9; // Start New Configuration 325 }; 326