1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 // Peripheral Memory 8 #define MT8167_XO_BASE 0x10000000 9 #define MT8167_XO_SIZE 0x2000 10 11 #define MT8167_GPIO_BASE 0x10005000 12 #define MT8167_GPIO_SIZE 0x700 13 14 #define MT8167_IOCFG_BASE 0x10005900 15 #define MT8167_IOCFG_SIZE 0x700 16 17 #define MT8167_SCPSYS_BASE 0x10006000 18 #define MT8167_SCPSYS_SIZE 0x1000 19 20 #define MT8167_EINT_BASE 0x1000B000 21 #define MT8167_EINT_SIZE 0x800 22 23 #define MT8167_SOC_BASE 0x10200000 24 #define MT8167_SOC_SIZE 0x1D00 25 26 #define MT8167_I2C0_BASE 0x11009000 27 #define MT8167_I2C0_SIZE 0x8c 28 29 #define MT8167_I2C1_BASE 0x1100a000 30 #define MT8167_I2C1_SIZE 0x8c 31 32 #define MT8167_I2C2_BASE 0x1100b000 33 #define MT8167_I2C2_SIZE 0x8c 34 35 #define MT8167_USB0_BASE 0x11100000 36 #define MT8167_USB0_LENGTH 0x1000 37 38 #define MT8167_USBPHY_BASE 0x11110800 39 #define MT8167_USBPHY_LENGTH 0x800 40 41 #define MT8167_MSDC0_BASE 0x11120000 42 #define MT8167_MSDC0_SIZE 0x22c 43 44 #define MT8167_MSDC2_BASE 0x11170000 45 #define MT8167_MSDC2_SIZE 0x22c 46 47 #define MT8167_MSDC2_GPIO_BASE 0x10005e40 48 #define MT8167_MSDC2_GPIO_SIZE 0x20 49 50 #define MT8167_MFG_BASE 0x13000000 51 #define MT8167_MFG_SIZE 0x80000 52 53 #define MT8167_MFG_TOP_CONFIG_BASE 0x13ffe000 54 #define MT8167_MFG_TOP_CONFIG_SIZE 0x1000 55 56 #define MT8167_AP_MIXED_SYS_BASE 0x10018000 57 #define MT8167_AP_MIXED_SYS_SIZE 0x714 58 59 #define MT8167_THERMAL_BASE 0x1100d000 60 #define MT8167_THERMAL_SIZE 0x510 61 62 #define MT8167_FUSE_BASE 0x10009000 63 #define MT8167_FUSE_SIZE 0x1000 64 65 #define MT8167_PMIC_WRAP_BASE 0x1000f000 66 #define MT8167_PMIC_WRAP_SIZE 0x1000 67 68 // Display Subsystem 69 #define MT8167_MSYS_CFG_BASE 0x14000000 70 #define MT8167_MSYS_CFG_SIZE 0x1000 71 #define MT8167_DISP_OVL_BASE 0x14007000 72 #define MT8167_DISP_OVL_SIZE 0x1000 73 #define MT8167_DISP_RDMA_BASE 0x14009000 74 #define MT8167_DISP_RDMA_SIZE 0x1000 75 #define MT8167_DISP_COLOR_BASE 0x1400C400 76 #define MT8167_DISP_COLOR_SIZE 0x900 77 #define MT8167_DITHER_BASE 0x14010000 78 #define MT8167_DITHER_SIZE 0x200 79 #define MT8167_DISP_DSI_BASE 0x14012000 80 #define MT8167_DISP_DSI_SIZE 0x200 81 #define MT8167_DISP_MUTEX_BASE 0x14015000 82 #define MT8167_DISP_MUTEX_SIZE 0x210 83 #define MT8167_MIPI_TX_BASE 0x14018000 84 #define MT8167_MIPI_TX_SIZE 0x100 85 #define MT8167_LVDS_BASE 0x1401A200 86 #define MT8167_LVDS_SIZE 0x100 87 88 // SOC Interrupt polarity registers start 89 #define MT8167_SOC_INT_POL 0x620 90 91 // MT8167s IRQ Table 92 #define MT8167_IRQ_USB_MCU 104 93 #define MT8167_IRQ_DISP_PWM 105 94 #define MT8167_IRQ_PWM 108 95 #define MT8167_IRQ_PTP_THERM 109 96 #define MT8167_IRQ_MSDC0 110 97 #define MT8167_IRQ_I2C0 112 98 #define MT8167_IRQ_I2C1 113 99 #define MT8167_IRQ_I2C2 114 100 #define MT8167_IRQ_UART0 116 101 #define MT8167_IRQ_UART1 117 102 #define MT8167_IRQ_MSDC2 141 103 #define MT8167_IRQ_HDMI_SIFM 142 104 #define MT8167_IRQ_ETHER_NIC_WRAP 143 105 #define MT8167_IRQ_ARM_EINT 166 106 #define MT8167_IRQ_DISP_OVL0 192 107 #define MT8167_IRQ_DISP_RDMA0 194 108 #define MT8167_IRQ_DISP_RDMA1 195 109 #define MT8167_IRQ_DISP_COLOR 197 110 #define MT8167_IRQ_DISP_DSI0 203 111 #define MT8167_IRQ_RGX 217 112 #define MT8167_IRQ_WDT 230 113 #define MT8167_IRQ_I2C3 241 114 #define MT8167_IRQ_UART2 243 115 116 #define MT8167_I2C_CNT 3 117 #define MT8167_GPIO_EINT_MAX 131 118 119 #define MT8167_GPIO_MT7668_PMU_EN 2 120 #define MT8167_GPIO_TOUCH_INT 8 121 #define MT8167_GPIO_TOUCH_RST 9 122 #define MT8167_GPIO_MSDC0_RST 114 123