1 // Copyright 2016 The Fuchsia Authors 2 // Copyright (c) 2016, Google, Inc. All rights reserved 3 // 4 // Use of this source code is governed by a MIT-style 5 // license that can be found in the LICENSE file or at 6 // https://opensource.org/licenses/MIT 7 8 9 #pragma once 10 11 #include <assert.h> 12 13 14 // TODO(cja): Find C users of this header and see if we can convert to pure 15 // C++ for it and use constexprs. 16 17 __BEGIN_CDECLS 18 19 /* 20 * PCI access return codes 21 */ 22 #define _PCI_SUCCESSFUL 0x00 23 #define _PCI_FUNC_NOT_SUPPORTED 0x81 24 #define _PCI_BAD_VENDOR_ID 0x83 25 #define _PCI_DEVICE_NOT_FOUND 0x86 26 #define _PCI_BAD_REGISTER_NUMBER 0x87 27 #define _PCI_SET_FAILED 0x88 28 #define _PCI_BUFFER_TOO_SMALL 0x89 29 30 /* 31 * PCI configuration space offsets 32 */ 33 #define PCI_CONFIG_VENDOR_ID 0x00 34 #define PCI_CONFIG_DEVICE_ID 0x02 35 #define PCI_CONFIG_COMMAND 0x04 36 #define PCI_CONFIG_STATUS 0x06 37 #define PCI_CONFIG_REVISION_ID 0x08 38 #define PCI_CONFIG_CLASS_CODE 0x09 39 #define PCI_CONFIG_CLASS_CODE_INTR 0x09 40 #define PCI_CONFIG_CLASS_CODE_SUB 0x0a 41 #define PCI_CONFIG_CLASS_CODE_BASE 0x0b 42 #define PCI_CONFIG_CACHE_LINE_SIZE 0x0c 43 #define PCI_CONFIG_LATENCY_TIMER 0x0d 44 #define PCI_CONFIG_HEADER_TYPE 0x0e 45 #define PCI_CONFIG_BIST 0x0f 46 #define PCI_CONFIG_BASE_ADDRESSES 0x10 47 #define PCI_CONFIG_CARDBUS_CIS_PTR 0x28 48 #define PCI_CONFIG_SUBSYS_VENDOR_ID 0x2c 49 #define PCI_CONFIG_SUBSYS_ID 0x2e 50 #define PCI_CONFIG_EXP_ROM_ADDRESS 0x30 51 #define PCI_CONFIG_CAPABILITIES 0x34 52 #define PCI_CONFIG_INTERRUPT_LINE 0x3c 53 #define PCI_CONFIG_INTERRUPT_PIN 0x3d 54 #define PCI_CONFIG_MIN_GRANT 0x3e 55 #define PCI_CONFIG_MAX_LATENCY 0x3f 56 57 /* 58 * PCI header type register bits 59 */ 60 #define PCI_HEADER_TYPE_MASK 0x7f 61 #define PCI_HEADER_TYPE_MULTI_FN 0x80 62 63 /* 64 * PCI header types 65 */ 66 #define PCI_HEADER_TYPE_STANDARD 0x00 67 #define PCI_HEADER_TYPE_PCI_BRIDGE 0x01 68 #define PCI_HEADER_TYPE_CARD_BUS 0x02 69 70 /* 71 * PCI command register bits 72 */ 73 #define PCI_COMMAND_IO_EN 0x0001 74 #define PCI_COMMAND_MEM_EN 0x0002 75 #define PCI_COMMAND_BUS_MASTER_EN 0x0004 76 #define PCI_COMMAND_SPECIAL_EN 0x0008 77 #define PCI_COMMAND_MEM_WR_INV_EN 0x0010 78 #define PCI_COMMAND_PAL_SNOOP_EN 0x0020 79 #define PCI_COMMAND_PERR_RESP_EN 0x0040 80 #define PCI_COMMAND_AD_STEP_EN 0x0080 81 #define PCI_COMMAND_SERR_EN 0x0100 82 #define PCI_COMMAND_FAST_B2B_EN 0x0200 83 84 85 /* 86 * PCI(e) general configuration definitions 87 */ 88 #define PCIE_MAX_BUSSES (256u) 89 #define PCIE_MAX_DEVICES_PER_BUS (32u) 90 #define PCIE_MAX_FUNCTIONS_PER_DEVICE (8u) 91 #define PCIE_MAX_FUNCTIONS_PER_BUS (PCIE_MAX_DEVICES_PER_BUS * PCIE_MAX_FUNCTIONS_PER_DEVICE) 92 93 #define PCIE_MAX_LEGACY_IRQ_PINS (4u) 94 #define PCIE_MAX_MSI_IRQS (32u) 95 #define PCIE_MAX_MSIX_IRQS (2048u) 96 97 #define PCIE_STANDARD_CONFIG_HDR_SIZE (64u) 98 #define PCIE_BASE_CONFIG_SIZE (256u) 99 #define PCIE_EXTENDED_CONFIG_SIZE (4096u) 100 #define PCIE_ECAM_BYTE_PER_BUS (PCIE_EXTENDED_CONFIG_SIZE * PCIE_MAX_FUNCTIONS_PER_BUS) 101 102 #define PCIE_BAR_REGS_PER_BRIDGE (2u) 103 #define PCIE_BAR_REGS_PER_DEVICE (6u) 104 #define PCIE_MAX_BAR_REGS (6u) 105 106 #define PCIE_INVALID_VENDOR_ID (0xFFFF) 107 108 /** 109 * The maximum possible number of standard capabilities for a PCI 110 * device/function is 48. This comes from the facts that... 111 * 112 * ++ There are 256 bytes in the standard configuration space. 113 * ++ The first 64 bytes are used by the standard configuration header, leaving 114 * 192 bytes for capabilities. 115 * ++ Even though the capability header is only 2 bytes long, it must be aligned 116 * on a 4 byte boundary. The means that one can pack (at most) 192 / 4 == 48 117 * properly aligned standard PCI capabilities. 118 * 119 * Similar logic may be applied to extended capabilities which must also be 4 120 * byte aligned, but exist in the region after the standard configuration block. 121 */ 122 #define PCIE_CAPABILITY_ALIGNMENT (4u) 123 124 #define PCIE_MAX_CAPABILITIES ((PCIE_BASE_CONFIG_SIZE - PCIE_STANDARD_CONFIG_HDR_SIZE) \ 125 / PCIE_CAPABILITY_ALIGNMENT) 126 #define PCIE_CAP_PTR_NULL (0u) 127 #define PCIE_CAP_PTR_MIN_VALID (PCIE_STANDARD_CONFIG_HDR_SIZE) 128 #define PCIE_CAP_PTR_MAX_VALID (PCIE_BASE_CONFIG_SIZE - PCIE_CAPABILITY_ALIGNMENT) 129 #define PCIE_CAP_PTR_ALIGNMENT (2u) 130 131 #define PCIE_EXT_CAP_PTR_NULL (0u) 132 #define PCIE_EXT_CAP_PTR_MIN_VALID (PCIE_BASE_CONFIG_SIZE) 133 #define PCIE_EXT_CAP_PTR_MAX_VALID (PCIE_EXTENDED_CONFIG_SIZE - PCIE_CAPABILITY_ALIGNMENT) 134 #define PCIE_EXT_CAP_PTR_ALIGNMENT (4u) 135 #define PCIE_MAX_EXT_CAPABILITIES ((PCIE_EXTENDED_CONFIG_SIZE - PCIE_BASE_CONFIG_SIZE) \ 136 / PCIE_CAPABILITY_ALIGNMENT) 137 138 /* 139 * PCI BAR register masks and constants 140 */ 141 #define PCI_BAR_IO_TYPE_MASK (0x00000001) 142 #define PCI_BAR_IO_TYPE_MMIO (0x00000000) 143 #define PCI_BAR_IO_TYPE_PIO (0x00000001) 144 145 #define PCI_BAR_MMIO_TYPE_MASK (0x00000006) 146 #define PCI_BAR_MMIO_TYPE_32BIT (0x00000000) 147 #define PCI_BAR_MMIO_TYPE_64BIT (0x00000004) 148 149 #define PCI_BAR_MMIO_PREFETCH_MASK (0x00000008) 150 #define PCI_BAR_MMIO_ADDR_MASK (0xFFFFFFF0) 151 #define PCI_BAR_PIO_ADDR_MASK (0xFFFFFFFC) 152 153 /* 154 * Extra bits used in the CFG command and status registers defined by PCIe. See 155 * the PCIe Base Specification, sections 7.5.1.1 and 7.5.1.2 156 */ 157 #define PCIE_CFG_COMMAND_INT_DISABLE ((uint16_t)(1 << 10)) 158 #define PCIE_CFG_STATUS_INT_STS ((uint16_t)(1 << 3)) 159 160 __END_CDECLS 161 162 #ifdef __cplusplus 163 enum class PciAddrSpace { MMIO, PIO }; 164 #if ARCH_X86 165 constexpr bool PCIE_HAS_IO_ADDR_SPACE = true; 166 constexpr uint64_t PCIE_PIO_ADDR_SPACE_MASK = 0xFFFF; 167 constexpr uint64_t PCIE_PIO_ADDR_SPACE_SIZE = 0x10000; 168 #else // #if (defined(ARCH_X86) && ARCH_X86) 169 constexpr bool PCIE_HAS_IO_ADDR_SPACE = false; 170 constexpr uint64_t PCIE_PIO_ADDR_SPACE_MASK = 0xFFFFFFFF; 171 constexpr uint64_t PCIE_PIO_ADDR_SPACE_SIZE = 0x100000000; 172 #endif // #if (defined(ARCH_X86) && ARCH_X86) 173 #endif // __cplusplus 174