1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #define S905D2_GPIO_BASE 0xff634400 8 #define S905D2_GPIO_LENGTH 0x400 9 #define S905D2_GPIO_A0_BASE 0xff800000 10 #define S905D2_GPIO_AO_LENGTH 0x1000 11 #define S905D2_GPIO_INTERRUPT_BASE 0xffd00000 12 #define S905D2_GPIO_INTERRUPT_LENGTH 0x10000 13 14 #define S905D2_MSR_CLK_BASE 0xffd18000 15 #define S905D2_MSR_CLK_LENGTH 0x1000 16 17 #define S905D2_TEMP_SENSOR_BASE 0xff634000 18 #define S905D2_TEMP_SENSOR_LENGTH 0x1000 19 20 #define S905D2_USB0_BASE 0xff500000 21 #define S905D2_USB0_LENGTH 0x100000 22 23 #define S905D2_DOS_BASE 0xff620000 24 #define S905D2_DOS_LENGTH 0x10000 25 26 #define S905D2_DMC_BASE 0xff638000 27 #define S905D2_DMC_LENGTH 0x1000 28 29 #define S905D2_USBCTRL_BASE 0xffe09000 30 #define S905D2_USBCTRL_LENGTH 0x2000 31 32 #define S905D2_RESET_BASE 0xffd01000 33 #define S905D2_RESET_LENGTH 0x1000 34 35 #define S905D2_MIPI_DSI_BASE 0xffd07000 36 #define S905D2_MIPI_DSI_LENGTH 0x1000 37 38 #define S905D2_DSI_PHY_BASE 0xff644000 39 #define S905D2_DSI_PHY_LENGTH 0x1000 40 41 #define S905D2_USBPHY20_BASE 0xff636000 42 #define S905D2_USBPHY20_LENGTH 0x2000 43 44 #define S905D2_USBPHY21_BASE 0xff63a000 45 #define S905D2_USBPHY21_LENGTH 0x2000 46 47 #define S905D2_HIU_BASE 0xff63c000 48 #define S905D2_HIU_LENGTH 0x2000 49 50 #define S905D2_VPU_BASE 0xff900000 51 #define S905D2_VPU_LENGTH 0x40000 52 53 #define S905D2_MALI_BASE 0xffe40000 54 #define S905D2_MALI_LENGTH 0x40000 55 56 #define S905D2_CBUS_BASE 0xffd00000 57 #define S905D2_CBUS_LENGTH 0x100000 58 #define S905D2_I2C0_BASE (S905D2_CBUS_BASE + 0x1f000) 59 #define S905D2_I2C1_BASE (S905D2_CBUS_BASE + 0x1e000) 60 #define S905D2_I2C2_BASE (S905D2_CBUS_BASE + 0x1d000) 61 #define S905D2_I2C3_BASE (S905D2_CBUS_BASE + 0x1c000) 62 63 #define S905D2_AOBUS_BASE 0xff800000 64 #define S905D2_AOBUS_LENGTH 0x100000 65 66 #define S905D2_I2C_AO_0_BASE (S905D2_AOBUS_BASE + 0x5000) 67 //SDIO 68 #define S905D2_EMMC_A_SDIO_BASE 0xffe03000 69 #define S905D2_EMMC_A_SDIO_LENGTH 0x2000 70 71 //PORT B 72 #define S905D2_EMMC_B_SDIO_BASE 0xffe05000 73 #define S905D2_EMMC_B_SDIO_LENGTH 0x2000 74 75 #define S905D2_RAW_NAND_REG_BASE (S905D2_AOBUS_BASE + 0x607800) 76 #define S905D2_RAW_NAND_CLOCK_BASE (S905D2_AOBUS_BASE + 0x607000) 77 78 #define S905D2_UART_A_BASE 0xffd24000 79 #define S905D2_UART_A_LENGTH 0x18 80 81 // Reset register offsets 82 #define S905D2_RESET0_REGISTER 0x04 83 #define S905D2_RESET1_REGISTER 0x08 84 #define S905D2_RESET1_USB (1 << 2) // bit to reset USB 85 #define S905D2_RESET2_REGISTER 0x0c 86 #define S905D2_RESET3_REGISTER 0x10 87 #define S905D2_RESET4_REGISTER 0x14 88 #define S905D2_RESET6_REGISTER 0x1c 89 #define S905D2_RESET7_REGISTER 0x20 90 #define S905D2_RESET0_MASK 0x40 91 #define S905D2_RESET1_MASK 0x44 92 #define S905D2_RESET2_MASK 0x48 93 #define S905D2_RESET3_MASK 0x4c 94 #define S905D2_RESET4_MASK 0x50 95 #define S905D2_RESET6_MASK 0x58 96 #define S905D2_RESET7_MASK 0x5c 97 #define S905D2_RESET0_LEVEL 0x80 98 #define S905D2_RESET1_LEVEL 0x84 99 #define S905D2_RESET2_LEVEL 0x88 100 #define S905D2_RESET3_LEVEL 0x8c 101 #define S905D2_RESET4_LEVEL 0x90 102 #define S905D2_RESET6_LEVEL 0x98 103 #define S905D2_RESET7_LEVEL 0x9c 104 105 #define S905D2_I2C0_IRQ 53 106 #define S905D2_I2C1_IRQ 246 107 #define S905D2_I2C2_IRQ 247 108 #define S905D2_I2C3_IRQ 71 109 #define S905D2_I2C_AO_0_IRQ 227 110 111 #define S905D2_PWM_BASE 0xffd00000 112 113 // PWM register offsets 114 // These are relative to base address S905D2_PWM_BASE and in sizeof(uint32_t) 115 #define S905D2_PWM_PWM_A 0x6c00 116 #define S905D2_PWM_PWM_B 0x6c01 117 #define S905D2_PWM_MISC_REG_AB 0x6c02 118 #define S905D2_DS_A_B 0x6c03 119 #define S905D2_PWM_TIME_AB 0x6c04 120 #define S905D2_PWM_A2 0x6c05 121 #define S905D2_PWM_B2 0x6c06 122 #define S905D2_PWM_BLINK_AB 0x6c07 123 124 #define S905D2_PWM_PWM_C 0x6800 125 #define S905D2_PWM_PWM_D 0x6801 126 #define S905D2_PWM_MISC_REG_CD 0x6802 127 #define S905D2_DS_C_D 0x6803 128 #define S905D2_PWM_TIME_CD 0x6804 129 #define S905D2_PWM_C2 0x6805 130 #define S905D2_PWM_D2 0x6806 131 #define S905D2_PWM_BLINK_CD 0x6807 132 133 #define S905D2_PWM_PWM_E 0x6400 134 #define S905D2_PWM_PWM_F 0x6401 135 #define S905D2_PWM_MISC_REG_EF 0x6402 136 #define S905D2_DS_E_F 0x6403 137 #define S905D2_PWM_TIME_EF 0x6404 138 #define S905D2_PWM_E2 0x6405 139 #define S905D2_PWM_F2 0x6406 140 #define S905D2_PWM_BLINK_EF 0x6407 141 142 #define S905D2_AO_PWM_AB_BASE 0xFF807000 143 #define S905D2_AO_PWM_CD_BASE 0xFF802000 144 #define S905D2_AO_PWM_LENGTH 0x1000 145 146 // Datasheet has incorrect number, but linux device tree seems correct. 147 #define S905D2_VIU1_VSYNC_IRQ 35 148 #define S905D2_DEMUX_IRQ 55 149 #define S905D2_UART_A_IRQ 58 150 #define S905D2_USB0_IRQ 62 151 #define S905D2_PARSER_IRQ 64 152 #define S905D2_RAW_NAND_IRQ 66 153 #define S905D2_TS_PLL_IRQ 67 154 #define S905D2_DOS_MBOX_0_IRQ 75 155 #define S905D2_DOS_MBOX_1_IRQ 76 156 #define S905D2_DOS_MBOX_2_IRQ 77 157 #define S905D2_GPIO_IRQ_0 96 158 #define S905D2_GPIO_IRQ_1 97 159 #define S905D2_GPIO_IRQ_2 98 160 #define S905D2_GPIO_IRQ_3 99 161 #define S905D2_GPIO_IRQ_4 100 162 #define S905D2_GPIO_IRQ_5 101 163 #define S905D2_GPIO_IRQ_6 102 164 #define S905D2_GPIO_IRQ_7 103 165 #define S905D2_RDMA_DONE 121 166 #define S905D2_MALI_IRQ_GP 192 167 #define S905D2_MALI_IRQ_GPMMU 193 168 #define S905D2_MALI_IRQ_PP 194 169 #define S905D2_A0_GPIO_IRQ_0 238 170 #define S905D2_A0_GPIO_IRQ_1 239 171 172 #define S905D2_EMMC_A_SDIO_IRQ 221 173 #define S905D2_EMMC_B_SDIO_IRQ 222 174 175 // Alternate Functions for SDIO 176 #define S905D2_WIFI_SDIO_D0 S905D2_GPIOX(0) 177 #define S905D2_WIFI_SDIO_D0_FN 1 178 #define S905D2_WIFI_SDIO_D1 S905D2_GPIOX(1) 179 #define S905D2_WIFI_SDIO_D1_FN 1 180 #define S905D2_WIFI_SDIO_D2 S905D2_GPIOX(2) 181 #define S905D2_WIFI_SDIO_D2_FN 1 182 #define S905D2_WIFI_SDIO_D3 S905D2_GPIOX(3) 183 #define S905D2_WIFI_SDIO_D3_FN 1 184 #define S905D2_WIFI_SDIO_CLK S905D2_GPIOX(4) 185 #define S905D2_WIFI_SDIO_CLK_FN 1 186 #define S905D2_WIFI_SDIO_CMD S905D2_GPIOX(5) 187 #define S905D2_WIFI_SDIO_CMD_FN 1 188 #define S905D2_WIFI_SDIO_WAKE_HOST S905D2_GPIOX(7) 189 #define S905D2_WIFI_SDIO_WAKE_HOST_FN 1 190 191 // Alternate functions for UARTs 192 #define S905D2_UART_TX_A S905D2_GPIOX(12) 193 #define S905D2_UART_TX_A_FN 1 194 #define S905D2_UART_RX_A S905D2_GPIOX(13) 195 #define S905D2_UART_RX_A_FN 1 196 #define S905D2_UART_CTS_A S905D2_GPIOX(14) 197 #define S905D2_UART_CTS_A_FN 1 198 #define S905D2_UART_RTS_A S905D2_GPIOX(15) 199 #define S905D2_UART_RTS_A_FN 1 200 201 // Alternate function for PWM 202 #define S905D2_PWM_D S905D2_GPIOE(1) 203 #define S905D2_PWM_D_FN 3 204 205 #define S905D2_EE_PDM_BASE (0xff640000) 206 #define S905D2_EE_PDM_LENGTH (0x2000) 207 208 #define S905D2_EE_AUDIO_BASE (0xff642000) 209 #define S905D2_EE_AUDIO_LENGTH (0x1000) 210 211 #define HHI_GCLK_MPEG0_OFFSET 0x50 212 #define HHI_SD_EMMC_CLK_CNTL_OFFSET 0x99 213