1 // Copyright 2018 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #pragma once
6
7 #include <assert.h>
8
9 #include <ddk/io-buffer.h>
10 #include <ddk/mmio-buffer.h>
11 #include <ddk/protocol/platform/device.h>
12
13 #include <hw/reg.h>
14 #include <lib/sync/completion.h>
15 #include <soc/aml-common/aml-rawnand.h>
16 #include <zircon/threads.h>
17 #include <zircon/types.h>
18
19 #include "onfi.h"
20
21 typedef enum raw_nand_addr_window {
22 NANDREG_WINDOW = 0,
23 CLOCKREG_WINDOW,
24 ADDR_WINDOW_COUNT, // always last
25 } raw_nand_addr_window_t;
26
27 typedef struct {
28 int ecc_strength;
29 int user_mode;
30 int rand_mode;
31 #define NAND_USE_BOUNCE_BUFFER 0x1
32 int options;
33 int bch_mode;
34 } aml_controller_t;
35
36 typedef struct {
37 onfi_callback_t onfi;
38 pdev_protocol_t pdev;
39 zx_device_t* zxdev;
40 mmio_buffer_t mmio[ADDR_WINDOW_COUNT];
41 thrd_t irq_thread;
42 zx_handle_t irq_handle;
43 bool enabled;
44 aml_controller_t controller_params;
45 uint32_t chip_select;
46 int chip_delay;
47 uint32_t writesize; /* NAND pagesize - bytes */
48 uint32_t erasesize; /* size of erase block - bytes */
49 uint32_t erasesize_pages;
50 uint32_t oobsize; /* oob bytes per NAND page - bytes */
51 #define NAND_BUSWIDTH_16 0x00000002
52 uint32_t bus_width; /* 16bit or 8bit ? */
53 uint64_t chipsize; /* MiB */
54 uint32_t page_shift; /* NAND page shift */
55 sync_completion_t req_completion;
56 struct {
57 uint64_t ecc_corrected;
58 uint64_t failed;
59 } stats;
60 io_buffer_t data_buffer;
61 io_buffer_t info_buffer;
62 zx_handle_t bti_handle;
63 void *info_buf, *data_buf;
64 zx_paddr_t info_buf_paddr, data_buf_paddr;
65 } aml_raw_nand_t;
66
set_bits(uint32_t * _reg,const uint32_t _value,const uint32_t _start,const uint32_t _len)67 static inline void set_bits(uint32_t* _reg, const uint32_t _value,
68 const uint32_t _start, const uint32_t _len) {
69 writel(((readl(_reg) & ~(((1L << (_len)) - 1) << (_start))) | ((uint32_t)((_value) & ((1L << (_len)) - 1)) << (_start))), _reg);
70 }
71
nandctrl_set_cfg(aml_raw_nand_t * raw_nand,uint32_t val)72 static inline void nandctrl_set_cfg(aml_raw_nand_t* raw_nand,
73 uint32_t val) {
74 volatile uint8_t* reg = (volatile uint8_t*)
75 raw_nand->mmio[NANDREG_WINDOW].vaddr;
76
77 writel(val, reg + P_NAND_CFG);
78 }
79
nandctrl_set_timing_async(aml_raw_nand_t * raw_nand,int bus_tim,int bus_cyc)80 static inline void nandctrl_set_timing_async(aml_raw_nand_t* raw_nand,
81 int bus_tim,
82 int bus_cyc) {
83 volatile uint8_t* reg = (volatile uint8_t*)
84 raw_nand->mmio[NANDREG_WINDOW].vaddr;
85
86 set_bits((uint32_t*)(reg + P_NAND_CFG),
87 ((bus_cyc & 31) | ((bus_tim & 31) << 5) | (0 << 10)),
88 0, 12);
89 }
90
nandctrl_send_cmd(aml_raw_nand_t * raw_nand,uint32_t cmd)91 static inline void nandctrl_send_cmd(aml_raw_nand_t* raw_nand,
92 uint32_t cmd) {
93 volatile uint8_t* reg = (volatile uint8_t*)
94 raw_nand->mmio[NANDREG_WINDOW].vaddr;
95
96 writel(cmd, reg + P_NAND_CMD);
97 }
98
99 /*
100 * Controller ECC, OOB, RAND parameters
101 */
102 struct aml_controller_params {
103 int ecc_strength; /* # of ECC bits per ECC page */
104 int user_mode; /* OOB bytes every ECC page or per block ? */
105 int rand_mode; /* Randomize ? */
106 int bch_mode;
107 };
108
109 /*
110 * In the case where user_mode == 2 (2 OOB bytes per ECC page),
111 * the controller adds one of these structs *per* ECC page in
112 * the info_buf.
113 */
114 struct __attribute__((packed)) aml_info_format {
115 uint16_t info_bytes;
116 uint8_t zero_bits; /* bit0~5 is valid */
117 struct ecc_sta {
118 uint8_t eccerr_cnt : 6;
119 uint8_t notused : 1;
120 uint8_t completed : 1;
121 } ecc;
122 uint32_t reserved;
123 };
124
125 static_assert(sizeof(struct aml_info_format) == 8,
126 "sizeof(struct aml_info_format) must be exactly 8 bytes");
127
128 typedef struct nand_setup {
129 union {
130 uint32_t d32;
131 struct {
132 unsigned cmd : 22;
133 unsigned large_page : 1;
134 unsigned no_rb : 1;
135 unsigned a2 : 1;
136 unsigned reserved25 : 1;
137 unsigned page_list : 1;
138 unsigned sync_mode : 2;
139 unsigned size : 2;
140 unsigned active : 1;
141 } b;
142 } cfg;
143 uint16_t id;
144 uint16_t max;
145 } nand_setup_t;
146
147 typedef struct _nand_cmd {
148 uint8_t type;
149 uint8_t val;
150 } nand_cmd_t;
151
152 typedef struct _ext_info {
153 uint32_t read_info;
154 uint32_t new_type;
155 uint32_t page_per_blk;
156 uint32_t xlc;
157 uint32_t ce_mask;
158 uint32_t boot_num;
159 uint32_t each_boot_pages;
160 uint32_t bbt_occupy_pages;
161 uint32_t bbt_start_block;
162 } ext_info_t;
163
164 typedef struct _nand_page0 {
165 nand_setup_t nand_setup;
166 unsigned char page_list[16];
167 nand_cmd_t retry_usr[32];
168 ext_info_t ext_info;
169 } nand_page0_t;
170
171 #define AML_PAGE0_LEN 384
172 /*
173 * Backup copies of page0 are located every 128 pages,
174 * with the last one at 896.
175 */
176 #define AML_PAGE0_STEP 128
177 #define AML_PAGE0_MAX_ADDR 896
178 /*
179 * NAND timing defaults
180 */
181 #define TREA_MAX_DEFAULT 20
182 #define RHOH_MIN_DEFAULT 15
183