1 // Copyright 2016 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #include <zircon/types.h> 8 9 __BEGIN_CDECLS 10 11 // ask clang format not to mess up the indentation: 12 // clang-format off 13 14 15 // Base Address Registers are accessed in userspace via the get_bar protocol method. The 16 // Bar is represented via a pci_bar_t struct which contains a handle pointer to a VMO 17 // in the case of an MMIO bar, as well as a PIO addr/size pair for the memory region 18 // to access if a PIO bar. In the latter case, the protocol will acquire the appropriate 19 // permissions for the process to write to that PIO region on that architecture. 20 typedef uint32_t zx_pci_bar_types_t; 21 #define ZX_PCI_BAR_TYPE_UNUSED ((zx_pci_bar_types_t) 0u) 22 #define ZX_PCI_BAR_TYPE_MMIO ((zx_pci_bar_types_t) 1u) 23 #define ZX_PCI_BAR_TYPE_PIO ((zx_pci_bar_types_t) 2u) 24 25 // TODO(cja): This makes some assumptions that anything in an arch's PIO region 26 // is going to be defined as a base address and size. This will need to be 27 // updated to a per-platform structure in the event that doesn't pan out 28 // in the future. 29 typedef struct zx_pci_bar { 30 uint32_t id; 31 uint32_t type; 32 size_t size; 33 union { 34 uintptr_t addr; 35 zx_handle_t handle; 36 }; 37 } zx_pci_bar_t; 38 39 // Defines and structures related to zx_pci_*() 40 // Info returned to dev manager for PCIe devices when probing. 41 typedef struct zx_pcie_device_info { 42 uint16_t vendor_id; 43 uint16_t device_id; 44 45 uint8_t base_class; 46 uint8_t sub_class; 47 uint8_t program_interface; 48 uint8_t revision_id; 49 50 uint8_t bus_id; 51 uint8_t dev_id; 52 uint8_t func_id; 53 } zx_pcie_device_info_t; 54 55 #define ZX_PCI_MAX_BUSSES (256u) 56 #define ZX_PCI_MAX_DEVICES_PER_BUS (32u) 57 #define ZX_PCI_MAX_FUNCTIONS_PER_DEVICE (8u) 58 #define ZX_PCI_MAX_FUNCTIONS_PER_BUS (ZX_PCI_MAX_DEVICES_PER_BUS * ZX_PCI_MAX_FUNCTIONS_PER_DEVICE) 59 60 #define ZX_PCI_MAX_LEGACY_IRQ_PINS (4u) 61 #define ZX_PCI_MAX_MSI_IRQS (32u) 62 #define ZX_PCI_MAX_MSIX_IRQS (2048u) 63 64 #define ZX_PCI_STANDARD_CONFIG_HDR_SIZE (64u) 65 #define ZX_PCI_BASE_CONFIG_SIZE (256u) 66 #define ZX_PCI_EXTENDED_CONFIG_SIZE (4096u) 67 #define ZX_PCI_ECAM_BYTE_PER_BUS (ZX_PCI_EXTENDED_CONFIG_SIZE * ZX_PCI_MAX_FUNCTIONS_PER_BUS) 68 69 #define ZX_PCI_BAR_REGS_PER_BRIDGE (2u) 70 #define ZX_PCI_BAR_REGS_PER_DEVICE (6u) 71 #define ZX_PCI_MAX_BAR_REGS (6u) 72 73 #define ZX_PCI_NO_IRQ_MAPPING UINT32_MAX 74 75 // Used for zx_pci_init_arg_t::addr_windows::cfg_space_type 76 #define PCI_CFG_SPACE_TYPE_PIO (0u) 77 #define PCI_CFG_SPACE_TYPE_MMIO (1u) 78 #define PCI_CFG_SPACE_TYPE_DW_ROOT (2u) // Designware Root Bridge ECAM 79 #define PCI_CFG_SPACE_TYPE_DW_DS (3u) // Designware Downstream ECAM 80 81 // Dimensions: device id, function id, legacy pin number 82 // ZX_PCI_NO_IRQ_MAPPING if no mapping specified. 83 typedef uint32_t zx_pci_irq_swizzle_lut_t[ZX_PCI_MAX_DEVICES_PER_BUS] 84 [ZX_PCI_MAX_FUNCTIONS_PER_DEVICE] 85 [ZX_PCI_MAX_LEGACY_IRQ_PINS]; 86 87 typedef struct zx_pci_init_arg { 88 zx_pci_irq_swizzle_lut_t dev_pin_to_global_irq; 89 90 uint32_t num_irqs; 91 struct { 92 uint32_t global_irq; 93 bool level_triggered; 94 bool active_high; 95 } irqs[64]; 96 97 uint32_t addr_window_count; 98 struct { 99 uint64_t base; 100 size_t size; 101 uint8_t bus_start; 102 uint8_t bus_end; 103 uint8_t cfg_space_type; 104 bool has_ecam; 105 } addr_windows[]; 106 } zx_pci_init_arg_t; 107 108 #define ZX_PCI_INIT_ARG_MAX_ECAM_WINDOWS 2 109 #define ZX_PCI_INIT_ARG_MAX_SIZE (sizeof(((zx_pci_init_arg_t*)NULL)->addr_windows[0]) * \ 110 ZX_PCI_INIT_ARG_MAX_ECAM_WINDOWS + \ 111 sizeof(zx_pci_init_arg_t)) 112 113 // Enum used to select PCIe IRQ modes 114 typedef uint32_t zx_pci_irq_mode_t; 115 #define ZX_PCIE_IRQ_MODE_DISABLED ((zx_pci_irq_mode_t) 0u) 116 #define ZX_PCIE_IRQ_MODE_LEGACY ((zx_pci_irq_mode_t) 1u) 117 #define ZX_PCIE_IRQ_MODE_MSI ((zx_pci_irq_mode_t) 2u) 118 #define ZX_PCIE_IRQ_MODE_MSI_X ((zx_pci_irq_mode_t) 3u) 119 120 __END_CDECLS 121