1 // Copyright 2016 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef ZIRCON_SYSCALLS_DEBUG_ 6 #define ZIRCON_SYSCALLS_DEBUG_ 7 8 #include <stdint.h> 9 #include <zircon/compiler.h> 10 11 __BEGIN_CDECLS 12 13 #if defined(__x86_64__) 14 15 // Value for ZX_THREAD_STATE_GENERAL_REGS on x86-64 platforms. 16 typedef struct zx_thread_state_general_regs { 17 uint64_t rax; 18 uint64_t rbx; 19 uint64_t rcx; 20 uint64_t rdx; 21 uint64_t rsi; 22 uint64_t rdi; 23 uint64_t rbp; 24 uint64_t rsp; 25 uint64_t r8; 26 uint64_t r9; 27 uint64_t r10; 28 uint64_t r11; 29 uint64_t r12; 30 uint64_t r13; 31 uint64_t r14; 32 uint64_t r15; 33 uint64_t rip; 34 uint64_t rflags; 35 } zx_thread_state_general_regs_t; 36 37 // Value for ZX_THREAD_STATE_FP_REGS on x64. Holds x87 and MMX state. 38 typedef struct zx_thread_state_fp_regs { 39 uint16_t fcw; // Control word. 40 uint16_t fsw; // Status word. 41 uint8_t ftw; // Tag word. 42 uint8_t reserved; 43 uint16_t fop; // Opcode. 44 uint64_t fip; // Instruction pointer. 45 uint64_t fdp; // Data pointer. 46 47 // The x87/MMX state. For x87 the each "st" entry has the low 80 bits used for the register 48 // contents. For MMX, the low 64 bits are used. The higher bits are unused. 49 __ALIGNED(16) 50 struct { 51 uint64_t low; 52 uint64_t high; 53 } st[8]; 54 } zx_thread_state_fp_regs_t; 55 56 // Value for ZX_THREAD_STATE_VECTOR_REGS on x64. Holds SSE and AVX registers. 57 // 58 // Setting vector registers will only work for threads that have previously executed an 59 // instruction using the corresponding register class. 60 typedef struct zx_thread_state_vector_regs { 61 // When only 16 registers are supported (pre-AVX-512), zmm[16-31] will be 0. 62 // YMM registers (256 bits) are v[0-4], XMM registers (128 bits) are v[0-2]. 63 struct { 64 uint64_t v[8]; 65 } zmm[32]; 66 67 // AVX-512 opmask registers. Will be 0 unless AVX-512 is supported. 68 uint64_t opmask[8]; 69 70 // SIMD control and status register. 71 uint32_t mxcsr; 72 } zx_thread_state_vector_regs_t; 73 74 // Value for ZX_THREAD_STATE_DEBUG_REGS on x64 platforms. 75 typedef struct zx_thread_state_debug_regs { 76 uint64_t dr[4]; 77 // DR4 and D5 are not used. 78 uint64_t dr6; // Status register. 79 uint64_t dr7; // Control register. 80 // TODO(donosoc): These values are deprecated but are still used by zxdb. We debine both values 81 // in order to do a soft transition. Delete these values once zxdb has made the 82 // update. 83 uint64_t dr6_status; // Status register. 84 uint64_t dr7_control; // Control register. 85 } zx_thread_state_debug_regs_t; 86 87 #elif defined(__aarch64__) 88 89 // Value for ZX_THREAD_STATE_GENERAL_REGS on ARM64 platforms. 90 typedef struct zx_thread_state_general_regs { 91 uint64_t r[30]; 92 uint64_t lr; 93 uint64_t sp; 94 uint64_t pc; 95 uint64_t cpsr; 96 } zx_thread_state_general_regs_t; 97 98 // Value for ZX_THREAD_STATE_FP_REGS on ARM64 platforms. 99 // This is unused because vector state is used for all floating point on ARM64. 100 typedef struct zx_thread_state_fp_regs { 101 // Avoids sizing differences for empty structs between C and C++. 102 uint32_t unused; 103 } zx_thread_state_fp_regs_t; 104 105 // Value for ZX_THREAD_STATE_VECTOR_REGS on ARM64 platforms. 106 typedef struct zx_thread_state_vector_regs { 107 uint32_t fpcr; 108 uint32_t fpsr; 109 struct { 110 uint64_t low; 111 uint64_t high; 112 } v[32]; 113 } zx_thread_state_vector_regs_t; 114 115 // ARMv8-A provides 2 to 16 hardware breakpoint registers. 116 // The number is obtained by the BRPs field in the EDDFR register. 117 #define AARCH64_MAX_HW_BREAKPOINTS 16 118 // ARMv8-A provides 2 to 16 watchpoint breakpoint registers. 119 // The number is obtained by the WRPs field in the EDDFR register. 120 #define AARCH64_MAX_HW_WATCHPOINTS 16 121 122 // Value for XZ_THREAD_STATE_DEBUG_REGS for ARM64 platforms. 123 typedef struct zx_thread_state_debug_regs { 124 struct { 125 uint64_t dbgbvr; // HW Breakpoint Value register. 126 uint32_t dbgbcr; // HW Breakpoint Control register. 127 } hw_bps[AARCH64_MAX_HW_BREAKPOINTS]; 128 // Number of HW Breakpoints in the platform. 129 // Will be set on read and ignored on write. 130 uint8_t hw_bps_count; 131 struct { 132 uint64_t dbgwvr; // HW Watchpoint Value register. 133 uint32_t dbgwcr; // HW Watchpoint Control register. 134 } hw_wps[AARCH64_MAX_HW_WATCHPOINTS]; 135 // Number of HW Watchpoints in the platform. 136 // Will be set on read and ignored on write. 137 uint8_t hw_wps_count; 138 } zx_thread_state_debug_regs_t; 139 140 #endif 141 142 // Value for ZX_THREAD_STATE_SINGLE_STEP. The value can be 0 (not single-stepping), or 1 143 // (single-stepping). Other values will give ZX_ERR_INVALID_ARGS. 144 typedef uint32_t zx_thread_state_single_step_t; 145 146 // Values for ZX_THREAD_X86_REGISTER_FS and ZX_THREAD_X86_REGISTER_GS; 147 typedef uint64_t zx_thread_x86_register_fs_t; 148 typedef uint64_t zx_thread_x86_register_gs_t; 149 150 // Possible values for "kind" in zx_thread_read_state and zx_thread_write_state. 151 typedef uint32_t zx_thread_state_topic_t; 152 #define ZX_THREAD_STATE_GENERAL_REGS ((uint32_t)0) // zx_thread_state_general_regs_t value. 153 #define ZX_THREAD_STATE_FP_REGS ((uint32_t)1) // zx_thread_state_fp_regs_t value. 154 #define ZX_THREAD_STATE_VECTOR_REGS ((uint32_t)2) // zx_thread_state_vector_regs_t value. 155 #define ZX_THREAD_STATE_DEBUG_REGS ((uint32_t)4) // zx_thread_state_debug_regs_t value. 156 #define ZX_THREAD_STATE_SINGLE_STEP ((uint32_t)5) // zx_thread_state_single_step_t value. 157 #define ZX_THREAD_X86_REGISTER_FS ((uint32_t)6) // zx_thread_x86_register_fs_t value. 158 #define ZX_THREAD_X86_REGISTER_GS ((uint32_t)7) // zx_thread_x86_register_gs_t value. 159 160 __END_CDECLS 161 162 #endif // ZIRCON_SYSCALLS_DEBUG_ 163