1 // Copyright 2018 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #pragma once
6 
7 // TOP MIPI_DSI AML Registers
8 #define MIPI_DSI_TOP_SW_RESET                   (0xF0 << 2)
9 #define MIPI_DSI_TOP_CLK_CNTL                   (0xF1 << 2)
10 #define MIPI_DSI_TOP_CNTL                       (0xF2 << 2)
11 #define MIPI_DSI_TOP_SUSPEND_CNTL               (0xF3 << 2)
12 #define MIPI_DSI_TOP_SUSPEND_LINE               (0xF4 << 2)
13 #define MIPI_DSI_TOP_SUSPEND_PIX                (0xF5 << 2)
14 #define MIPI_DSI_TOP_MEAS_CNTL                  (0xF6 << 2)
15 #define MIPI_DSI_TOP_STAT                       (0xF7 << 2)
16 #define MIPI_DSI_TOP_MEAS_STAT_TE0              (0xF8 << 2)
17 #define MIPI_DSI_TOP_MEAS_STAT_TE1              (0xF9 << 2)
18 #define MIPI_DSI_TOP_MEAS_STAT_VS0              (0xFA << 2)
19 #define MIPI_DSI_TOP_MEAS_STAT_VS1              (0xFB << 2)
20 #define MIPI_DSI_TOP_INTR_CNTL_STAT             (0xFC << 2)
21 #define MIPI_DSI_TOP_MEM_PD                     (0xFD << 2)
22 
23 #define MIPI_DSI_PHY_CTRL                       (0x000 << 2)
24 #define MIPI_DSI_CHAN_CTRL                      (0x001 << 2)
25 #define MIPI_DSI_CHAN_STS                       (0x002 << 2)
26 #define MIPI_DSI_CLK_TIM                        (0x003 << 2)
27 #define MIPI_DSI_HS_TIM                         (0x004 << 2)
28 #define MIPI_DSI_LP_TIM                         (0x005 << 2)
29 #define MIPI_DSI_ANA_UP_TIM                     (0x006 << 2)
30 #define MIPI_DSI_INIT_TIM                       (0x007 << 2)
31 #define MIPI_DSI_WAKEUP_TIM                     (0x008 << 2)
32 #define MIPI_DSI_LPOK_TIM                       (0x009 << 2)
33 #define MIPI_DSI_LP_WCHDOG                      (0x00a << 2)
34 #define MIPI_DSI_ANA_CTRL                       (0x00b << 2)
35 #define MIPI_DSI_CLK_TIM1                       (0x00c << 2)
36 #define MIPI_DSI_TURN_WCHDOG                    (0x00d << 2)
37 #define MIPI_DSI_ULPS_CHECK                     (0x00e << 2)
38 #define MIPI_DSI_TEST_CTRL0                     (0x00f << 2)
39 #define MIPI_DSI_TEST_CTRL1                     (0x010 << 2)
40 
41 // MIPI_DSI_TOP_CNTL Bit definitions
42 #define TOP_CNTL_DPI_CLR_MODE_START             (20)
43 #define TOP_CNTL_DPI_CLR_MODE_BITS              (4)
44 #define TOP_CNTL_IN_CLR_MODE_START              (16)
45 #define TOP_CNTL_IN_CLR_MODE_BITS               (3)
46 #define TOP_CNTL_CHROMA_SUBSAMPLE_START         (14)
47 #define TOP_CNTL_CHROMA_SUBSAMPLE_BITS          (2)
48 
49 // MIPI_DSI_PHY_CTRL Bit definitions
50 #define PHY_CTRL_TXDDRCLK_EN                    (1 << 0)
51 #define PHY_CTRL_DDRCLKPATH_EN                  (1 << 7)
52 #define PHY_CTRL_CLK_DIV_COUNTER                (1 << 8)
53 #define PHY_CTRL_CLK_DIV_EN                     (1 << 9)
54 #define PHY_CTRL_BYTECLK_EN                     (1 << 12)
55 #define PHY_CTRL_RST_START                      (31)
56 #define PHY_CTRL_RST_BITS                       (1)
57 
58 #define ANA_UP_TIME                             (0x100) // from vendor
59 #define LPOK_TIME                               (0x7C)
60 #define ULPS_CHECK_TIME                         (0x927C)
61 #define LP_WCHDOG_TIME                          (0x1000)
62 #define TURN_WCHDOG_TIME                        (0x1000)
63 
64 // Frequency Ranges (in KHz) specific to AmLogic S905D2
65 #define FIN_FREQ_KHZ                            (24 * 1000)
66 #define MIN_PLL_VCO_KHZ                         (3000 * 1000)
67 #define MAX_PLL_VCO_KHZ                         (6000 * 1000)
68 #define MIN_PLL_FREQ_KHZ                        (MIN_PLL_VCO_KHZ / 16)
69 #define MAX_PLL_FREQ_KHZ                        (MAX_PLL_VCO_KHZ)
70 #define MAX_PIXEL_CLK_KHZ                       (200 * 1000)
71 #define MAX_OD_SEL                              (3)
72 #define PLL_FRAC_RANGE                          (1 << 17)
73 
74 // We currently only support 8 bit mode
75 #define SUPPORTED_LCD_BITS                      (8)
76 #define SUPPORTED_DPI_FORMAT                    (MIPI_DSI_COLOR_24BIT)
77 #define SUPPORTED_VENC_DATA_WIDTH               (MIPI_DSI_VENC_COLOR_24B)
78 #define SUPPORTED_VIDEO_MODE_TYPE               (VID_MODE_TYPE_BURST_MODE)
79 
80 // AML PHY Timer Config Values
81 #define PHY_TMR_LPCLK_CLKHS_TO_LP               (0x87)
82 #define PHY_TMR_LPCLK_CLKLP_TO_HS               (0x25)
83 #define PHY_TMR_HS_TO_LP                        (0x0332)
84 #define PHY_TMR_LP_TO_HS                        (0x0)
85 #define DPHY_TIMEOUT                            (200000)
86 
87 // This defined the number of bytes of the largest packet that can fit in LP mode during
88 // various regions (VSA, VBP, VFP, VACT).
89 #define LPCMD_PKT_SIZE                          (4)
90 
91 
92 // The following values are based on MIPI D-PHY Spec Version 2.1 Table 14. The
93 // values defined are recommended values coming from AmLogic
94 
95 // x100 multiplier to ensure proper ui value
96 #define UI_X_100                                (100)
97 // Time that the transmitter continues to send HS clock after the last associated Data Lane
98 // has transitioned to LP Mode. Interval is defined as the period from the end of HS-Trail
99 // to the beginning of CLK-TRAIL (>60+52*ui)
100 #define DPHY_TIME_CLK_POST(ui)                  (2 * (60 * UI_X_100 + 52 * ui))
101 
102 // Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane
103 // beginging the transition from LP to HS mode.  (>8*ui)
104 #define DPHY_TIME_CLK_PRE(ui)                   (10 * ui)
105 
106 // Time that the transmitter drives the Clock Lane LP-00 Line state immediately
107 // before the HS-0 Line state starting the HS transmission (38, 95)
108 #define DPHY_TIME_CLK_PREPARE                   (50 * UI_X_100)
109 
110 // Time that the transmitter drives the HS-0 state after the last payload clock bit of a
111 // HS transmission burst  (>60ns)
112 #define DPHY_TIME_CLK_TRAIL                     (70 * UI_X_100)
113 
114 // CLK-PREPARE + time the transmitter drives the HS-0 state prior to starting the Clock (> 300)
115 #define DPHY_TIME_CLK_ZERO(ui)                  (320 * UI_X_100 - DPHY_TIME_CLK_PREPARE)
116 
117 // Transmitted time internal from the start of HS-TRAIL or CLK-TRAIL to start of
118 // LP-11 state following a HS burst
119 #define DPHY_TIME_EOT(ui)                       (105 * UI_X_100 + 12 * ui)
120 
121 // Time that the transmitter drives the LP-11 following a HS burst (>100ns)
122 #define DPHY_TIME_HS_EXIT                       (110 * UI_X_100)
123 
124 // Time that the transmitter drives the Data Lane LP-00 Line state immediately
125 // before the HS-0 Line state starting the HS transmission (40+4*ui, 85+6*ui)
126 #define DPHY_TIME_HS_PREPARE(ui)                (50 * UI_X_100 + 4 * ui)
127 
128 // HS_PREPARE + time that the transmitter drives the HS-0 state prior to transmitting
129 // the Sync sequence  (>145+10*ui)
130 #define DPHY_TIME_HS_ZERO(ui)               (160 * UI_X_100  + 10 * ui - DPHY_TIME_HS_PREPARE(ui))
131 
132 // Time that the transmitter drives the flipped differential state after last
133 // payload data bit of a HS transmissoin burst  max(n*8*ui, 60+n*4*ui) <n = 1>
134 #define DPHY_TIME_HS_TRAIL(ui)                  (fbl::max((8 * ui), (60 * UI_X_100  + 4 * ui)))
135 
136 // >100us
137 #define DPHY_TIME_INIT                          (110 * UI_X_100  * 1000)
138 
139 // TX length of any LP state should be >50ns according to MIPI D-PHY Spec
140 #define DPHY_TIME_LP_LPX                        (100 * UI_X_100 )
141 
142 // Time that the new transmitter drives the Bridge state (LP-00) after
143 // accepting control during a Link Trunaround (5*lpx)
144 #define DPHY_TIME_LP_TA_GET                     (5 * DPHY_TIME_LP_LPX)
145 
146 // Time that the transmitter drives the Bridge state (LP-00) before releasing
147 // control during a Link Turnaround  (4*lpx)
148 #define DPHY_TIME_LP_TA_GO                      (4 * DPHY_TIME_LP_LPX)
149 
150 // Time that the new transmitter waits after the LP-10 state before transmitting
151 // the Bridge state (LP-00) during a Link Turnaround (lpx, 2*lpx)
152 #define DPHY_TIME_LP_TA_SURE                    (DPHY_TIME_LP_LPX)
153 
154 // Time that a transmitter drives a Mark-1 state prior to a Stop state in order to initiate an
155 // exit from ULPS >1ms
156 #define DPHY_TIME_WAKEUP                        (1020 * UI_X_100 * 1000)
157 
158 // LP TX excape mode should be  >100ns --> TODO(payamm): Where is this coming from?
159 #define DPHY_TIME_LP_TESC                       (250 * UI_X_100 )
160 
161 //  MIPI DSI/VENC Color Format Definitions
162 #define MIPI_DSI_VENC_COLOR_24B                 (0x1)
163 
164 // This structure holds the parameters used to program VPU LCD interface
165 struct LcdTiming {
166     uint32_t vid_pixel_on;
167     uint32_t vid_line_on;
168     uint32_t de_hs_addr;
169     uint32_t de_he_addr;
170     uint32_t de_vs_addr;
171     uint32_t de_ve_addr;
172     uint32_t hs_hs_addr;
173     uint32_t hs_he_addr;
174     uint32_t hs_vs_addr;
175     uint32_t hs_ve_addr;
176     uint32_t vs_hs_addr;
177     uint32_t vs_he_addr;
178     uint32_t vs_vs_addr;
179     uint32_t vs_ve_addr;
180 };
181 
182 // This structure holds the calculated pll values based on desired pixel clock
183 struct PllConfig { // unit: kHz
184     // IN-OUT parameters
185     uint32_t fin;
186     uint32_t fout;
187 
188     // calculated bitrate
189     uint32_t bitrate;
190 
191     // pll parameters
192     uint32_t pll_m;
193     uint32_t pll_n;
194     uint32_t pll_fvco;
195     uint32_t pll_od1_sel;
196     uint32_t pll_od2_sel;
197     uint32_t pll_od3_sel;
198     uint32_t pll_frac;
199     uint32_t pll_fout;
200 };
201