1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #include <hwreg/bitfields.h> 6 #include <zircon/types.h> 7 8 #pragma once 9 10 // clang-format off 11 12 // Register offset 13 #define AML_TRIM_INFO 0x268 14 #define AML_HHI_TS_CLK_CNTL 0x64 << 2 15 #define AML_TS_CFG_REG1 (0x800 + (0x1 << 2)) 16 #define AML_TS_CFG_REG2 (0x800 + (0x2 << 2)) 17 #define AML_TS_CFG_REG3 (0x800 + (0x3 << 2)) 18 #define AML_TS_CFG_REG4 (0x800 + (0x4 << 2)) 19 #define AML_TS_CFG_REG5 (0x800 + (0x5 << 2)) 20 #define AML_TS_CFG_REG6 (0x800 + (0x6 << 2)) 21 #define AML_TS_CFG_REG7 (0x800 + (0x7 << 2)) 22 #define AML_TS_CFG_REG8 (0x800 + (0x8 << 2)) 23 #define AML_TS_STAT0 (0x800 + (0x10 << 2)) 24 #define AML_TS_STAT1 (0x800 + (0x11 << 2)) 25 #define IRQ_FALL_ENABLE_SHIFT 28 26 #define IRQ_RISE_ENABLE_SHIFT 24 27 #define IRQ_FALL_STAT_CLR_SHIFT 20 28 #define IRQ_RISE_STAT_CLR_SHIFT 16 29 #define AML_RISE_THRESHOLD_IRQ 0xf 30 #define AML_FALL_THRESHOLD_IRQ 0xf0 31 #define AML_TEMP_CAL 1 32 #define AML_TS_TEMP_MASK 0xfff 33 #define AML_TS_CH_SEL 0x3 /* set 3'b011 for work */ 34 #define AML_HHI_TS_CLK_ENABLE 0x130U /* u-boot */ 35 #define MCELSIUS 1000 36 #define AML_TS_VALUE_CONT 0x10 37 #define AML_TS_REBOOT_TIME 0xff 38 39 //clang-format on 40 41 namespace thermal { 42 43 class TsCfgReg1 : public hwreg::RegisterBase<TsCfgReg1, uint32_t> { 44 public: 45 DEF_BIT(31, fall_th3_irq_en); 46 DEF_BIT(30, fall_th2_irq_en); 47 DEF_BIT(29, fall_th1_irq_en); 48 DEF_BIT(28, fall_th0_irq_en); 49 DEF_BIT(27, rise_th3_irq_en); 50 DEF_BIT(26, rise_th2_irq_en); 51 DEF_BIT(25, rise_th1_irq_en); 52 DEF_BIT(24, rise_th0_irq_en); 53 DEF_BIT(23, fall_th3_irq_stat_clr); 54 DEF_BIT(22, fall_th2_irq_stat_clr); 55 DEF_BIT(21, fall_th1_irq_stat_clr); 56 DEF_BIT(20, fall_th0_irq_stat_clr); 57 DEF_BIT(19, rise_th3_irq_stat_clr); 58 DEF_BIT(18, rise_th2_irq_stat_clr); 59 DEF_BIT(17, rise_th1_irq_stat_clr); 60 DEF_BIT(16, rise_th0_irq_stat_clr); 61 DEF_BIT(15, enable_irq); 62 DEF_BIT(14, fast_mode); 63 DEF_BIT(13, clr_hi_temp_stat); 64 DEF_BIT(12, ts_ana_rset_vbg); 65 DEF_BIT(11, ts_ana_rset_sd); 66 DEF_BIT(10, ts_ana_en_vcm); 67 DEF_BIT(9, ts_ana_en_vbg); 68 DEF_FIELD(8, 7, filter_hcic_mode); 69 DEF_BIT(6, filter_ts_out_ctrl); 70 DEF_BIT(5, filter_en); 71 DEF_BIT(4, ts_ena_en_iptat); 72 DEF_BIT(3, ts_dem_en); 73 DEF_FIELD(2, 0, bipolar_bias_current_input); 74 Get()75 static auto Get() { return hwreg::RegisterAddr<TsCfgReg1>(AML_TS_CFG_REG1); } 76 }; 77 78 class TsCfgReg2 : public hwreg::RegisterBase<TsCfgReg2, uint32_t> { 79 public: 80 DEF_BIT(31, hi_temp_enable); 81 DEF_BIT(30, reset_en); 82 DEF_FIELD(27, 16, high_temp_times); 83 DEF_FIELD(15, 0, high_temp_threshold); 84 Get()85 static auto Get() { return hwreg::RegisterAddr<TsCfgReg2>(AML_TS_CFG_REG2); } 86 }; 87 88 class TsCfgReg4 : public hwreg::RegisterBase<TsCfgReg4, uint32_t> { 89 public: 90 DEF_FIELD(23, 12, rise_th0); 91 DEF_FIELD(11, 0, rise_th1); 92 Get()93 static auto Get() { return hwreg::RegisterAddr<TsCfgReg4>(AML_TS_CFG_REG4); } 94 }; 95 96 class TsCfgReg5 : public hwreg::RegisterBase<TsCfgReg5, uint32_t> { 97 public: 98 DEF_FIELD(23, 12, rise_th0); 99 DEF_FIELD(11, 0, rise_th1); 100 Get()101 static auto Get() { return hwreg::RegisterAddr<TsCfgReg5>(AML_TS_CFG_REG5); } 102 }; 103 104 class TsCfgReg6 : public hwreg::RegisterBase<TsCfgReg6, uint32_t> { 105 public: 106 DEF_FIELD(23, 12, fall_th0); 107 DEF_FIELD(11, 0, fall_th1); 108 Get()109 static auto Get() { return hwreg::RegisterAddr<TsCfgReg6>(AML_TS_CFG_REG6); } 110 }; 111 112 class TsCfgReg7 : public hwreg::RegisterBase<TsCfgReg7, uint32_t> { 113 public: 114 DEF_FIELD(23, 12, fall_th0); 115 DEF_FIELD(11, 0, fall_th1); 116 Get()117 static auto Get() { return hwreg::RegisterAddr<TsCfgReg7>(AML_TS_CFG_REG7); } 118 }; 119 120 class TsStat0 : public hwreg::RegisterBase<TsStat0, uint32_t> { 121 public: 122 DEF_FIELD(15, 0, temperature); 123 Get()124 static auto Get() { return hwreg::RegisterAddr<TsStat0>(AML_TS_STAT0); } 125 }; 126 127 class TsStat1 : public hwreg::RegisterBase<TsStat1, uint32_t> { 128 public: 129 DEF_BIT(8, hi_temp_stat); 130 DEF_BIT(7, fall_th3_irq); 131 DEF_BIT(6, fall_th2_irq); 132 DEF_BIT(5, fall_th1_irq); 133 DEF_BIT(4, fall_th0_irq); 134 DEF_BIT(3, rise_th3_irq); 135 DEF_BIT(2, rise_th2_irq); 136 DEF_BIT(1, rise_th1_irq); 137 DEF_BIT(0, rise_th0_irq); 138 Get()139 static auto Get() { return hwreg::RegisterAddr<TsStat1>(AML_TS_STAT1); } 140 }; 141 142 143 } // namespace thermal 144