1 // Copyright 2016 The Fuchsia Authors 2 // Copyright (c) 2016, Google, Inc. All rights reserved 3 // 4 // Use of this source code is governed by a MIT-style 5 // license that can be found in the LICENSE file or at 6 // https://opensource.org/licenses/MIT 7 8 #pragma once 9 10 #include <dev/pcie_bus_driver.h> 11 #include <dev/pcie_ref_counted.h> 12 #include <dev/pcie_upstream_node.h> 13 #include <zircon/compiler.h> 14 #include <fbl/macros.h> 15 #include <fbl/intrusive_wavl_tree.h> 16 #include <fbl/ref_ptr.h> 17 18 class PcieRoot : public fbl::WAVLTreeContainable<fbl::RefPtr<PcieRoot>>, 19 public PcieUpstreamNode 20 { 21 public: 22 // Disallow copying, assigning and moving. 23 DISALLOW_COPY_ASSIGN_AND_MOVE(PcieRoot); 24 25 // Implement ref counting, do not let derived classes override. 26 PCIE_IMPLEMENT_REFCOUNTED; 27 28 // Properties driver()29 PcieBusDriver& driver() { return bus_drv_; } pf_mmio_regions()30 RegionAllocator& pf_mmio_regions() final { return bus_drv_.pf_mmio_regions(); } mmio_lo_regions()31 RegionAllocator& mmio_lo_regions() final { return bus_drv_.mmio_lo_regions(); } mmio_hi_regions()32 RegionAllocator& mmio_hi_regions() final { return bus_drv_.mmio_hi_regions(); } pio_regions()33 RegionAllocator& pio_regions() final { return bus_drv_.pio_regions(); } 34 35 // Perform the swizzle for the root which this swizzle interface applies to. 36 // 37 // When legacy IRQs traverse PCI/PCIe roots, they are subject to a platform 38 // specific IRQ swizzle operation. Platforms must supply an implementation 39 // of this method for when they add a root to the bus driver before startup. 40 // 41 // @param dev_id The device ID of the pcie device/bridge to swizzle for. 42 // @param func_id The function ID of the pcie device/bridge to swizzle for. 43 // @param pin The pin we want to swizzle 44 // @param irq An output pointer for what IRQ this pin goes to 45 // 46 // @return ZX_OK if we successfully swizzled 47 // @return ZX_ERR_NOT_FOUND if we did not know how to swizzle this pin 48 virtual zx_status_t Swizzle(uint dev_id, uint func_id, uint pin, uint *irq) = 0; 49 50 // WAVL-tree Index GetKey()51 uint GetKey() const { return managed_bus_id(); } 52 // TODO(johngro) : Add support for RCRB (root complex register block) Consider splitting 53 // PcieRoot into PciRoot and PcieRoot (since PciRoots don't have RCRBs) 54 55 protected: 56 PcieRoot(PcieBusDriver& bus_drv, uint mbus_id); 57 58 private: 59 PcieBusDriver& bus_drv_; 60 }; 61