1 // Copyright 2018 The Fuchsia Authors
2 //
3 // Use of this source code is governed by a MIT-style
4 // license that can be found in the LICENSE file or at
5 // https://opensource.org/licenses/MIT
6 
7 #pragma once
8 
9 #include <arch/x86/page_tables/page_tables.h>
10 #include "hw.h"
11 
12 namespace intel_iommu {
13 
14 class DeviceContext;
15 class IommuImpl;
16 
17 // Implementation of second-level page tables used by VT-d
18 class SecondLevelPageTable final : public X86PageTableBase {
19 public:
20     SecondLevelPageTable(IommuImpl* iommu, DeviceContext* parent);
21     ~SecondLevelPageTable();
22 
23     zx_status_t Init(PageTableLevel top_level);
24     void Destroy();
25 private:
top_level()26     PageTableLevel top_level() final { return top_level_; }
27     bool allowed_flags(uint flags) final;
28     bool check_paddr(paddr_t paddr) final;
29     bool check_vaddr(vaddr_t vaddr) final;
30     bool supports_page_size(PageTableLevel level) final;
31     IntermediatePtFlags intermediate_flags() final;
32     PtFlags terminal_flags(PageTableLevel level, uint flags) final;
33     PtFlags split_flags(PageTableLevel level, PtFlags flags) final;
34     void TlbInvalidate(PendingTlbInvalidation* pending) final;
35     uint pt_flags_to_mmu_flags(PtFlags flags, PageTableLevel level) final;
needs_cache_flushes()36     bool needs_cache_flushes() final { return needs_flushes_; }
37 
38     IommuImpl* iommu_;
39     DeviceContext* parent_;
40 
41     PageTableLevel top_level_;
42     bool needs_flushes_;
43     bool supports_2mb_;
44     bool supports_1gb_;
45 
46     vaddr_t valid_vaddr_mask_;
47     bool initialized_;
48 };
49 
50 } // namespace intel_iommu
51