| /kernel/dev/pcie/ |
| A D | pci_config.cpp | 20 constexpr PciReg16 PciConfig::kVendorId;
21 constexpr PciReg16 PciConfig::kDeviceId;
22 constexpr PciReg16 PciConfig::kCommand;
23 constexpr PciReg16 PciConfig::kStatus;
26 constexpr PciReg8 PciConfig::kSubClass;
27 constexpr PciReg8 PciConfig::kBaseClass;
31 constexpr PciReg8 PciConfig::kBist;
45 constexpr PciReg8 PciConfig::kIoBase;
77 friend PciConfig;
123 friend PciConfig;
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| A D | pcie_bridge.cpp | 83 uint primary_id = cfg_->Read(PciConfig::kPrimaryBusId); in Init()
134 base = cfg_->Read(PciConfig::kIoBase); in ParseBusWindowsLocked()
135 limit = cfg_->Read(PciConfig::kIoLimit); in ParseBusWindowsLocked()
152 base = cfg_->Read(PciConfig::kPrefetchableMemoryBase); in ParseBusWindowsLocked()
153 limit = cfg_->Read(PciConfig::kPrefetchableMemoryLimit); in ParseBusWindowsLocked()
305 cfg_->Write(PciConfig::kIoBase, 0xF0); in Disable()
306 cfg_->Write(PciConfig::kIoLimit, 0); in Disable()
307 cfg_->Write(PciConfig::kIoBaseUpper, 0); in Disable()
308 cfg_->Write(PciConfig::kIoLimitUpper, 0); in Disable()
310 cfg_->Write(PciConfig::kMemoryBase, 0xFFF0); in Disable()
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| A D | debug.cpp | 325 uint8_t base_class = cfg->Read(PciConfig::kBaseClass); in dump_pcie_common()
327 LSPCI_PRINTF("Command : 0x%04x\n", cfg->Read(PciConfig::kCommand)); in dump_pcie_common()
328 LSPCI_PRINTF("Status : 0x%04x\n", cfg->Read(PciConfig::kStatus)); in dump_pcie_common()
337 LSPCI_PRINTF("BIST : 0x%02x\n", cfg->Read(PciConfig::kBist)); in dump_pcie_common()
350 LSPCI_PRINTF("Min Grant : 0x%02x\n", cfg->Read(PciConfig::kMinGrant)); in dump_pcie_standard()
351 LSPCI_PRINTF("Max Latency : 0x%02x\n", cfg->Read(PciConfig::kMaxLatency)); in dump_pcie_standard()
363 LSPCI_PRINTF("IO Base : 0x%02x\n", cfg->Read(PciConfig::kIoBase)); in dump_pcie_bridge()
365 LSPCI_PRINTF("IO Limit : 0x%02x\n", cfg->Read(PciConfig::kIoLimit)); in dump_pcie_bridge()
374 LSPCI_PRINTF("Memory Base : 0x%04x", cfg->Read(PciConfig::kMemoryBase)); in dump_pcie_bridge()
398 static void dump_pcie_raw_config(uint amt, const PciConfig* cfg) in dump_pcie_raw_config()
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| A D | pcie_device.cpp | 132 vendor_id_ = cfg_->Read(PciConfig::kVendorId); in InitLocked()
133 device_id_ = cfg_->Read(PciConfig::kDeviceId); in InitLocked()
134 class_id_ = cfg_->Read(PciConfig::kBaseClass); in InitLocked()
135 subclass_ = cfg_->Read(PciConfig::kSubClass); in InitLocked()
137 rev_id_ = cfg_->Read(PciConfig::kRevisionId); in InitLocked()
269 cmd_backup = cfg_->Read(PciConfig::kCommand); in DoFunctionLevelReset()
294 cfg_->Write(PciConfig::kCommand, cmd_backup); in DoFunctionLevelReset()
327 cfg_->Write(PciConfig::kCommand, cmd_backup); in DoFunctionLevelReset()
364 cfg_->Write(PciConfig::kCommand, in ModifyCmdLocked()
467 cfg_->Write(PciConfig::kBAR(bar_id), bar_val); in ProbeBarLocked()
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| A D | pcie_upstream_node.cpp | 82 uint16_t vendor_id = cfg->Read(PciConfig::kVendorId); in ScanDownstream()
85 uint16_t device_id = cfg->Read(PciConfig::kDeviceId); in ScanDownstream()
115 (!good_device || !(cfg->Read(PciConfig::kHeaderType) & PCI_HEADER_TYPE_MULTI_FN))) in ScanDownstream()
121 fbl::RefPtr<PcieDevice> PcieUpstreamNode::ScanDevice(const PciConfig* cfg, in ScanDevice()
136 uint16_t vendor_id = cfg->Read(PciConfig::kVendorId); in ScanDevice()
145 uint8_t header_type = cfg->Read(PciConfig::kHeaderType) & PCI_HEADER_TYPE_MASK; in ScanDevice()
147 uint secondary_id = cfg->Read(PciConfig::kSecondaryBusId); in ScanDevice()
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| A D | pcie_irqs.cpp | 140 command = cfg->Read(PciConfig::kCommand); in Handler()
141 status = cfg->Read(PciConfig::kStatus); in Handler()
166 command = cfg->Read(PciConfig::kCommand); in Handler()
167 cfg->Write(PciConfig::kCommand, command | PCIE_CFG_COMMAND_INT_DISABLE); in Handler()
177 command = cfg->Read(PciConfig::kCommand); in Handler()
178 cfg->Write(PciConfig::kCommand, command | PCIE_CFG_COMMAND_INT_DISABLE); in Handler()
195 dev.cfg_->Write(PciConfig::kCommand, dev.cfg_->Read(PciConfig::kCommand) | in AddDevice()
214 dev.cfg_->Write(PciConfig::kCommand, dev.cfg_->Read(PciConfig::kCommand) | in RemoveDevice()
895 irq_.legacy.pin = cfg_->Read(PciConfig::kInterruptPin); in InitLegacyIrqStateLocked()
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| A D | pcie_bus_driver.cpp | 503 const PciConfig* PcieBusDriver::GetConfig(uint bus_id, in GetConfig()
530 auto cfg_iter = configs_.find_if([addr](const PciConfig& cfg) { in GetConfig()
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| A D | pcie_caps.cpp | 279 uint8_t cap_offset = cfg_->Read(PciConfig::kCapabilitiesPtr); in ParseStdCapabilitiesLocked()
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| /kernel/dev/pcie/address_provider/ |
| A D | pio.cpp | 19 fbl::RefPtr<PciConfig> PioPcieAddressProvider::CreateConfig(const uintptr_t addr) { in CreateConfig()
20 return PciConfig::Create(addr, PciAddrSpace::PIO); in CreateConfig()
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| A D | designware.cpp | 128 fbl::RefPtr<PciConfig> DesignWarePcieAddressProvider::CreateConfig(const uintptr_t addr) { in CreateConfig()
132 return PciConfig::Create(addr, PciAddrSpace::MMIO); in CreateConfig()
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| A D | mmio.cpp | 110 fbl::RefPtr<PciConfig> MmioPcieAddressProvider::CreateConfig(const uintptr_t addr) { in CreateConfig()
111 return PciConfig::Create(addr, PciAddrSpace::MMIO); in CreateConfig()
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| /kernel/dev/pcie/include/dev/address_provider/ |
| A D | address_provider.h | 35 virtual fbl::RefPtr<PciConfig> CreateConfig(const uintptr_t addr) = 0;
51 fbl::RefPtr<PciConfig> CreateConfig(const uintptr_t addr) override;
67 fbl::RefPtr<PciConfig> CreateConfig(const uintptr_t addr) override;
81 fbl::RefPtr<PciConfig> CreateConfig(const uintptr_t addr) override;
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| /kernel/dev/pcie/include/dev/ |
| A D | pci_config.h | 54 class PciConfig : public fbl::SinglyLinkedListable<fbl::RefPtr<PciConfig>>
55 , public fbl::RefCounted<PciConfig> {
121 static fbl::RefPtr<PciConfig> Create(uintptr_t base, PciAddrSpace addr_type);
133 virtual ~PciConfig(){}; in ~PciConfig()
136 PciConfig(uintptr_t base, PciAddrSpace addr_space) in PciConfig() function
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| A D | pcie_upstream_node.h | 19 class PciConfig; variable
61 fbl::RefPtr<PcieDevice> ScanDevice(const PciConfig* cfg, uint dev_id, uint func_id);
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| A D | pcie_bridge.h | 22 class PciConfig; variable
89 fbl::RefPtr<PcieDevice> ScanDevice(const PciConfig* cfg, uint dev_id, uint func_id);
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| A D | pcie_bus_driver.h | 29 class PciConfig; variable
60 const PciConfig* GetConfig(uint bus_id,
204 fbl::SinglyLinkedList<fbl::RefPtr<PciConfig>> configs_;
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| A D | pcie_device.h | 291 const PciConfig* config() const { return cfg_; } in config()
362 const PciConfig* cfg_ = nullptr; // Pointer to the memory mapped ECAM (kernel vaddr)
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