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Searched refs:UARTREG (Results 1 – 8 of 8) sorted by relevance

/kernel/dev/uart/pl011/
A Duart.cpp41 #define UARTREG(base, reg) (*REG32((base) + (reg))) macro
65 UARTREG(uart_base, UART_IMSC) &= ~(1 << 5); in pl011_mask_tx()
69 UARTREG(uart_base, UART_IMSC) |= (1 << 5); in pl011_unmask_tx()
74 uint32_t isr = UARTREG(uart_base, UART_TMIS); in pl011_uart_irq()
112 UARTREG(uart_base, UART_ICR) = 0x3ff; in pl011_uart_init()
122 UARTREG(uart_base, UART_CR) |= (1 << 9); // rxen in pl011_uart_init()
149 while (UARTREG(uart_base, UART_FR) & (1 << 5)) in pl011_uart_pputc()
151 UARTREG(uart_base, UART_DR) = c; in pl011_uart_pputc()
158 return UARTREG(uart_base, UART_DR); in pl011_uart_pgetc()
189 UARTREG(uart_base, UART_DR) = '\r'; in pl011_dputs()
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/kernel/dev/uart/amlogic_s905/
A Duart.cpp70 #define UARTREG(base, reg) (*(volatile uint32_t*)((base) + (reg))) macro
119 char c = static_cast<char>(UARTREG(base, S905_UART_RFIFO)); in uart_irq()
143 UARTREG(s905_uart_base, S905_UART_CONTROL) |= S905_UART_CONTROL_RSTRX | in s905_uart_init()
150 UARTREG(s905_uart_base, S905_UART_CONTROL) |= S905_UART_CONTROL_TXEN | in s905_uart_init()
159 UARTREG(s905_uart_base, S905_UART_CONTROL) |= val; in s905_uart_init()
162 uint32_t temp2 = UARTREG(s905_uart_base, S905_UART_IRQ_CONTROL); in s905_uart_init()
165 UARTREG(s905_uart_base, S905_UART_IRQ_CONTROL) = temp2; in s905_uart_init()
193 UARTREG(s905_uart_base, S905_UART_WFIFO) = c; in s905_uart_pputc()
204 return UARTREG(s905_uart_base, S905_UART_RFIFO); in s905_uart_pgetc()
263 UARTREG(s905_uart_base, S905_UART_WFIFO) = '\r'; in s905_dputs()
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/kernel/dev/uart/nxp-imx/
A Duart.cpp88 char c = UARTREG(MX8_URXD) & 0xFF; in uart_irq_handler()
93 if (UARTREG(MX8_UCR1) & UCR1_TRDYEN) { in uart_irq_handler()
112 while (UARTREG(MX8_UTS) & UTS_TXFULL) in imx_uart_pputc()
114 UARTREG(MX8_UTXD) = c; in imx_uart_pputc()
128 return UARTREG(MX8_URXD); in imx_uart_pgetc()
206 regVal = UARTREG(MX8_UFCR); in imx_uart_init()
211 UARTREG(MX8_UFCR) = regVal; in imx_uart_init()
214 regVal = UARTREG(MX8_UCR1); in imx_uart_init()
220 UARTREG(MX8_UCR1) = regVal; in imx_uart_init()
223 regVal = UARTREG(MX8_UCR2); in imx_uart_init()
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/kernel/target/arm64/boot-shim/
A Dimx8mevk-uart.c12 #define UARTREG(reg) (*(volatile uint32_t*)(0x30860000 + (reg))) macro
15 while (UARTREG(MX8_UTS) & UTS_TXFULL) in uart_pputc()
17 UARTREG(MX8_UTXD) = c; in uart_pputc()
A Dimx8mmevk-uart.c12 #define UARTREG(reg) (*(volatile uint32_t*)(0x30890000 + (reg))) macro
15 while (UARTREG(MX8_UTS) & UTS_TXFULL) in uart_pputc()
17 UARTREG(MX8_UTXD) = c; in uart_pputc()
A Dsherlock-uart.c12 #define UARTREG(reg) (*(volatile uint32_t*)(0xff803000 + (reg))) macro
15 while (UARTREG(S905_UART_STATUS) & S905_UART_STATUS_TXFULL) in uart_pputc()
17 UARTREG(S905_UART_WFIFO) = c; in uart_pputc()
A Dmt8167s_ref-uart.c12 #define UARTREG(reg) (*(volatile uint32_t*)(0x11005000 + (reg))) macro
15 while (!(UARTREG(UART_LSR) & UART_LSR_THRE)) in uart_pputc()
17 UARTREG(UART_THR) = c; in uart_pputc()
/kernel/dev/uart/mt8167/
A Duart.cpp109 #define UARTREG(reg) (*(volatile uint32_t*)((uart_base) + (reg))) macro
114 while (UARTREG(UART_LSR) & UART_LSR_DR) { in uart_irq_handler()
118 char c = UARTREG(UART_RBR) & 0xFF; in uart_irq_handler()
123 if (UARTREG(UART_LSR) & UART_LSR_THRE) { in uart_irq_handler()
124 UARTREG(UART_IER) &= ~UART_IER_ETBEI; // Disable TX interrupt in uart_irq_handler()
143 while (!(UARTREG(UART_LSR) & UART_LSR_THRE)) in mt8167_uart_pputc()
145 UARTREG(UART_THR) = c; in mt8167_uart_pputc()
156 while (!(UARTREG(UART_LSR) & UART_LSR_DR)) in mt8167_uart_pgetc()
158 return UARTREG(UART_RBR); in mt8167_uart_pgetc()
193 while (!(UARTREG(UART_LSR) & UART_LSR_THRE)) { in mt8167_dputs()
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