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Searched refs:uint (Results 1 – 25 of 164) sorted by relevance

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/kernel/lib/gfx/include/lib/
A Dgfx.h48 uint width;
57 … void (*copyrect)(struct gfx_surface*, uint x, uint y, uint width, uint height, uint x2, uint y2);
58 void (*fillrect)(struct gfx_surface*, uint x, uint y, uint width, uint height, uint color);
59 void (*putpixel)(struct gfx_surface*, uint x, uint y, uint color);
61 uint ch, uint x, uint y, uint fg, uint bg);
62 void (*flush)(uint starty, uint endy);
69 void gfx_copyrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint x2, uint y2);
72 void gfx_fillrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint color);
75 void gfx_putpixel(gfx_surface* surface, uint x, uint y, uint color);
78 void gfx_line(gfx_surface* surface, uint x1, uint y1, uint x2, uint y2, uint color);
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/kernel/vm/include/vm/
A Darch_vm_aspace.h15 const uint ARCH_MMU_FLAG_CACHED = (0u << 0);
16 const uint ARCH_MMU_FLAG_UNCACHED = (1u << 0);
19 const uint ARCH_MMU_FLAG_CACHE_MASK = (3u << 0);
20 const uint ARCH_MMU_FLAG_PERM_USER = (1u << 2);
21 const uint ARCH_MMU_FLAG_PERM_READ = (1u << 3);
22 const uint ARCH_MMU_FLAG_PERM_WRITE = (1u << 4);
23 const uint ARCH_MMU_FLAG_PERM_EXECUTE = (1u << 5);
26 const uint ARCH_MMU_FLAG_NS = (1u << 6); // NON-SECURE
29 const uint ARCH_ASPACE_FLAG_KERNEL = (1u << 0);
30 const uint ARCH_ASPACE_FLAG_GUEST = (1u << 1);
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A Dfault.h14 const uint VMM_PF_FLAG_WRITE = (1u << 0);
15 const uint VMM_PF_FLAG_USER = (1u << 1);
16 const uint VMM_PF_FLAG_GUEST = (1u << 2);
17 const uint VMM_PF_FLAG_INSTRUCTION = (1u << 3);
18 const uint VMM_PF_FLAG_NOT_PRESENT = (1u << 4);
19 const uint VMM_PF_FLAG_HW_FAULT = (1u << 5); // hardware is requesting a fault
20 const uint VMM_PF_FLAG_SW_FAULT = (1u << 6); // software fault
21 const uint VMM_PF_FLAG_FAULT_MASK = (VMM_PF_FLAG_HW_FAULT | VMM_PF_FLAG_SW_FAULT);
24 static const char* vmm_pf_flags_to_string(uint pf_flags, char str[5]) { in vmm_pf_flags_to_string()
35 zx_status_t vmm_page_fault_handler(vaddr_t addr, uint pf_flags);
A Dpmm.h19 uint flags;
20 uint priority;
38 zx_status_t pmm_alloc_pages(size_t count, uint alloc_flags, list_node* list) __NONNULL((3));
41 zx_status_t pmm_alloc_page(uint alloc_flags, vm_page** p) __NONNULL((2));
42 zx_status_t pmm_alloc_page(uint alloc_flags, paddr_t* pa) __NONNULL((2));
43 zx_status_t pmm_alloc_page(uint alloc_flags, vm_page** p, paddr_t* pa) __NONNULL((2, 3));
51 zx_status_t pmm_alloc_contiguous(size_t count, uint alloc_flags, uint8_t align_log2,
A Dvm_aspace.h39 static fbl::RefPtr<VmAspace> Create(uint flags, const char* name);
128 static const uint VMM_FLAG_VALLOC_SPECIFIC = (1u << 0); // allocate at specific address
129 …static const uint VMM_FLAG_COMMIT = (1u << 1); // commit memory up front (no demand pagin…
137 paddr_t paddr, uint vmm_flags,
138 uint arch_mmu_flags);
140 uint vmm_flags, uint arch_mmu_flags);
142 uint vmm_flags, uint arch_mmu_flags);
148 size_t size, void** ptr, uint8_t align_pow2, uint vmm_flags,
149 uint arch_mmu_flags);
184 zx_status_t PageFault(vaddr_t va, uint flags);
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/kernel/include/
A Dpow2.h19 __CONSTEXPR static inline __ALWAYS_INLINE bool ispow2(uint val) in ispow2()
26 __CONSTEXPR static inline __ALWAYS_INLINE uint _log2_uint(uint val, bool ceiling) in _log2_uint()
31 uint log2 = (uint)(sizeof(val) * CHAR_BIT) - 1 - __builtin_clz(val); in _log2_uint()
41 __CONSTEXPR static inline __ALWAYS_INLINE uint log2_uint_floor(uint val) in log2_uint_floor()
47 __CONSTEXPR static inline __ALWAYS_INLINE uint log2_uint_ceil(uint val) in log2_uint_ceil()
59 uint log2 = (uint)(sizeof(val) * CHAR_BIT) - 1 - __builtin_clzl(val); in _log2_ulong()
69 __CONSTEXPR static inline __ALWAYS_INLINE uint log2_ulong_floor(ulong val) in log2_ulong_floor()
75 __CONSTEXPR static inline __ALWAYS_INLINE uint log2_ulong_ceil(ulong val) in log2_ulong_ceil()
80 __CONSTEXPR static inline __ALWAYS_INLINE uint valpow2(uint valp2) in valpow2()
85 __CONSTEXPR static inline __ALWAYS_INLINE uint divpow2(uint val, uint divp2) in divpow2()
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/kernel/arch/arm64/include/arch/
A Daspace.h63 uint index_shift, uint page_size_shift,
67 uint index_shift, uint page_size_shift,
71 pte_t attrs, uint index_shift, uint page_size_shift,
74 void MmuParamsFromFlags(uint mmu_flags,
76 uint* top_size_shift, uint* top_index_shift,
77 uint* page_size_shift);
79 vaddr_t vaddr_base, uint top_size_shift, uint top_index_shift,
80 uint page_size_shift) TA_REQ(lock_);
83 uint top_size_shift, uint top_index_shift,
88 uint top_index_shift, uint page_size_shift) TA_REQ(lock_);
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/kernel/arch/arm64/
A Dmp.cpp25 uint arm64_cpu_cluster_ids[SMP_MAX_CPUS] = {0};
26 uint arm64_cpu_cpu_ids[SMP_MAX_CPUS] = {0};
29 uint arm_num_cpus = 1;
35 void arch_init_cpu_map(uint cluster_count, const uint* cluster_cpus) { in arch_init_cpu_map()
39 uint cpu_id = 0; in arch_init_cpu_map()
41 uint cpus = *cluster_cpus++; in arch_init_cpu_map()
43 for (uint cpu = 0; cpu < cpus; cpu++) { in arch_init_cpu_map()
62 static uint arch_curr_cpu_num_slow() { in arch_curr_cpu_num_slow()
70 cpu_num_t arch_mpid_to_cpu_num(uint cluster, uint cpu) { in arch_mpid_to_cpu_num()
102 uint cpu = arch_curr_cpu_num_slow(); in arm64_init_percpu_early()
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/kernel/lib/pow2_range_allocator/include/lib/
A Dpow2_range_allocator.h38 uint bucket_count;
50 zx_status_t p2ra_init(p2ra_state_t* state, uint max_alloc_size);
76 zx_status_t p2ra_add_range(p2ra_state_t* state, uint range_start, uint range_len);
100 zx_status_t p2ra_allocate_range(p2ra_state_t* state, uint size, uint* out_range_start);
109 void p2ra_free_range(p2ra_state_t* state, uint range_start, uint size);
/kernel/arch/arm64/include/arch/arm64/
A Dmp.h44 void arch_init_cpu_map(uint cluster_count, const uint* cluster_cpus);
82 static inline uint arch_max_num_cpus(void) { in arch_max_num_cpus()
83 extern uint arm_num_cpus; in arch_max_num_cpus()
89 static inline uint arch_cpu_num_to_cluster_id(uint cpu) { in arch_cpu_num_to_cluster_id()
90 extern uint arm64_cpu_cluster_ids[SMP_MAX_CPUS]; in arch_cpu_num_to_cluster_id()
96 static inline uint arch_cpu_num_to_cpu_id(uint cpu) { in arch_cpu_num_to_cpu_id()
97 extern uint arm64_cpu_cpu_ids[SMP_MAX_CPUS]; in arch_cpu_num_to_cpu_id()
102 cpu_num_t arch_mpid_to_cpu_num(uint cluster, uint cpu);
/kernel/dev/pcie/include/dev/
A Dpcie_device.h50 uint first_bar_reg;
64 static fbl::RefPtr<PcieDevice> Create(PcieUpstreamNode& upstream, uint dev_id, uint func_id);
281 zx_status_t MaskUnmaskIrq(uint irq_id, bool mask);
307 uint bus_id() const { return bus_id_; } in bus_id()
308 uint dev_id() const { return dev_id_; } in dev_id()
333 PcieDevice(PcieBusDriver& bus_drv, uint bus_id, uint dev_id, uint func_id, bool is_bridge);
342 zx_status_t ProbeBarLocked(uint bar_id);
387 const uint bar_count_;
420 zx_status_t EnterMsiIrqMode(uint requested_irqs);
445 uint handler_count = 0;
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A Dpcie_irqs.h65 uint max_irqs; /** The maximum number of IRQ supported by the selected mode */
93 uint max_handlers; /// The max number of handlers for the mode.
94 uint registered_handlers; /// The current number of registered handlers.
113 uint irq_id,
124 uint pci_irq_id;
136 static fbl::RefPtr<SharedLegacyIrqHandler> Create(uint irq_id);
142 uint irq_id() const { return irq_id_; } in irq_id()
148 explicit SharedLegacyIrqHandler(uint irq_id);
160 const uint irq_id_;
A Dpcie_root.h48 virtual zx_status_t Swizzle(uint dev_id, uint func_id, uint pin, uint *irq) = 0;
51 uint GetKey() const { return managed_bus_id(); } in GetKey()
56 PcieRoot(PcieBusDriver& bus_drv, uint mbus_id);
A Dpcie_bridge.h27 uint dev_id,
28 uint func_id,
29 uint managed_bus_id);
68 PcieBridge(PcieBusDriver& bus_drv, uint bus_id, uint dev_id, uint func_id, uint mbus_id);
89 fbl::RefPtr<PcieDevice> ScanDevice(const PciConfig* cfg, uint dev_id, uint func_id);
A Dpcie_upstream_node.h38 fbl::RefPtr<PcieDevice> GetDownstream(uint ndx) { return bus_drv_.GetDownstream(*this, ndx); } in GetDownstream()
42 uint managed_bus_id() const { return managed_bus_id_; } in managed_bus_id()
51 PcieUpstreamNode(PcieBusDriver& bus_drv, Type type, uint mbus_id) in PcieUpstreamNode()
61 fbl::RefPtr<PcieDevice> ScanDevice(const PciConfig* cfg, uint dev_id, uint func_id);
67 const uint managed_bus_id_; // The ID of the downstream bus which this node manages.
/kernel/dev/interrupt/arm_gic/v2/
A Darm_gicv2m.cpp31 static uint g_reg_frame_count;
50 for (uint i = 0; i < g_reg_frame_count; ++i) { in arm_gicv2m_init()
52 uint base_spi = (type_reg >> 16) & 0x3FF; in arm_gicv2m_init()
53 uint num_spi = type_reg & 0x3FF; in arm_gicv2m_init()
57 for (uint i = 0; i < num_spi; ++i) { in arm_gicv2m_init()
58 uint spi_id = base_spi + i; in arm_gicv2m_init()
65 uint reg_ndx = spi_id >> 4; in arm_gicv2m_init()
66 uint bit_shift = ((spi_id & 0xF) << 1) + 1; in arm_gicv2m_init()
90 uint base_spi = (type_reg >> 16) & 0x3FF; in arm_gicv2m_get_frame_info()
91 uint num_spi = type_reg & 0x3FF; in arm_gicv2m_get_frame_info()
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/kernel/lib/gfx/
A Dgfx.cpp95 void gfx_copyrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint x2, uint y2) { in gfx_copyrect()
126 void gfx_fillrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint color) { in gfx_fillrect()
150 void gfx_putpixel(gfx_surface* surface, uint x, uint y, uint color) { in gfx_putpixel()
160 static void putpixel(gfx_surface* surface, uint x, uint y, uint color) { in putpixel()
172 static void copyrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint x2, uint y… in copyrect()
208 static void fillrect(gfx_surface* surface, uint x, uint y, uint width, uint height, uint _color) { in fillrect()
219 uint i, j; in fillrect()
229 void gfx_line(gfx_surface* surface, uint x1, uint y1, uint x2, uint y2, uint color) { in gfx_line()
424 uint ch, uint x, uint y, uint fg, uint bg) { in putchar()
440 uint ch, uint x, uint y, uint fg, uint bg) { in gfx_putchar()
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/kernel/tests/
A Dsync_ipi_tests.cpp30 uint cpu_num = arch_curr_cpu_num(); in inorder_count_task()
61 for (uint i = 0; i < fbl::count_of(threads); ++i) { in deadlock_test()
73 for (uint i = 0; i < fbl::count_of(threads); ++i) { in deadlock_test()
84 uint num_cpus = arch_max_num_cpus(); in sync_ipi_tests()
85 uint online = mp_get_online_mask(); in sync_ipi_tests()
91 uint runs = TEST_RUNS; in sync_ipi_tests()
94 for (uint i = 0; i < runs; ++i) { in sync_ipi_tests()
97 for (uint i = 0; i < num_cpus; ++i) { in sync_ipi_tests()
104 for (uint i = 0; i < runs; ++i) { in sync_ipi_tests()
116 ASSERT((uint)counter == num_cpus - 1); in sync_ipi_tests()
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/kernel/include/dev/
A Ddisplay.h34 uint width;
35 uint height;
36 uint stride;
41 void (*flush)(uint starty, uint endy);
/kernel/lib/libc/
A Diovec.c21 ssize_t iovec_size(const iovec_t* iov, uint iov_cnt) { in iovec_size()
27 for (uint i = 0; i < iov_cnt; i++, iov++) { in iovec_size()
37 ssize_t iovec_to_membuf(uint8_t* buf, uint buf_len, const iovec_t* iov, uint iov_cnt, uint iov_pos)… in iovec_to_membuf()
38 uint buf_pos = 0; in iovec_to_membuf()
45 for (uint i = 0; i < iov_cnt; i++, iov++) { in iovec_to_membuf()
/kernel/platform/pc/include/platform/pc/
A Dhpet.h25 zx_status_t hpet_timer_configure_irq(uint n, uint irq);
26 zx_status_t hpet_timer_set_oneshot(uint n, uint64_t deadline);
27 zx_status_t hpet_timer_set_periodic(uint n, uint64_t period);
28 zx_status_t hpet_timer_disable(uint n);
/kernel/include/lk/
A Dinit.h19 typedef void (*lk_init_hook)(uint level);
48 void lk_init_level(enum lk_init_flags flags, uint start_level, uint stop_level);
50 static inline void lk_primary_cpu_init_level(uint start_level, uint stop_level) in lk_primary_cpu_init_level()
61 uint level;
62 uint flags;
/kernel/arch/x86/include/arch/
A Daspace.h42 PtFlags terminal_flags(PageTableLevel level, uint flags) final;
45 uint pt_flags_to_mmu_flags(PtFlags flags, PageTableLevel level) final;
59 bool allowed_flags(uint flags) final;
64 PtFlags terminal_flags(PageTableLevel level, uint flags) final;
67 uint pt_flags_to_mmu_flags(PtFlags flags, PageTableLevel level) final;
76 zx_status_t Init(vaddr_t base, size_t size, uint mmu_flags) override;
82 uint mmu_flags, size_t* mapped) override;
89 vaddr_t PickSpot(vaddr_t base, uint prev_region_mmu_flags,
90 vaddr_t end, uint next_region_mmu_flags,
91 vaddr_t align, size_t size, uint mmu_flags) override;
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/kernel/dev/interrupt/arm_gic/v2/include/dev/interrupt/
A Darm_gicv2m.h19 uint start_spi_id; /** The first valid SPI ID in the frame */
20 uint end_spi_id; /** The last valid SPI ID in the frame */
34 void arm_gicv2m_init(const paddr_t* reg_frames, const vaddr_t* reg_frames_virt, uint reg_frame_coun…
49 zx_status_t arm_gicv2m_get_frame_info(uint frame_ndx, arm_gicv2m_frame_info_t* out_info);
/kernel/lib/libc/include/
A Diovec.h21 ssize_t iovec_size(const iovec_t *iov, uint iov_cnt);
23 ssize_t iovec_to_membuf(uint8_t *buf, uint buf_len,
24 const iovec_t *iov, uint iov_cnt, uint iov_pos);

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