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Searched refs:write_msr (Results 1 – 17 of 17) sorted by relevance

/kernel/arch/x86/
A Dproc_trace.cpp159 write_msr(IA32_RTIT_CTL, 0); in x86_ipt_set_mode_task()
160 write_msr(IA32_RTIT_STATUS, 0); in x86_ipt_set_mode_task()
161 write_msr(IA32_RTIT_OUTPUT_BASE, 0); in x86_ipt_set_mode_task()
162 write_msr(IA32_RTIT_OUTPUT_MASK_PTRS, 0); in x86_ipt_set_mode_task()
164 write_msr(IA32_RTIT_CR3_MATCH, 0); in x86_ipt_set_mode_task()
253 write_msr(IA32_RTIT_CTL, state->ctl); in x86_ipt_start_cpu_task()
313 write_msr(IA32_RTIT_CTL, 0); in x86_ipt_stop_cpu_task()
323 write_msr(IA32_RTIT_STATUS, 0); in x86_ipt_stop_cpu_task()
324 write_msr(IA32_RTIT_OUTPUT_BASE, 0); in x86_ipt_stop_cpu_task()
325 write_msr(IA32_RTIT_OUTPUT_MASK_PTRS, 0); in x86_ipt_stop_cpu_task()
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A Dhwp.cpp24 write_msr(X86_MSR_IA32_PM_ENABLE, 1); in hwp_enable_sync_task()
30 write_msr(X86_MSR_IA32_HWP_REQUEST, hwp_req); in hwp_enable_sync_task()
55 write_msr(X86_MSR_IA32_HWP_REQUEST, hwp_req); in hwp_set_hint_sync_task()
A Dmmu_mem_types.cpp169 write_msr(X86_MSR_IA32_MTRR_DEF_TYPE, 0); in x86_pat_sync_task()
172 write_msr(X86_MSR_IA32_MTRR_FIX64K_00000, target_mtrrs->mtrr_fix64k); in x86_pat_sync_task()
174 write_msr(IA32_MTRR_FIX16K_80000(i), target_mtrrs->mtrr_fix16k[i]); in x86_pat_sync_task()
177 write_msr(IA32_MTRR_FIX4K_C0000(i), target_mtrrs->mtrr_fix4k[i]); in x86_pat_sync_task()
180 write_msr(IA32_MTRR_PHYSBASE(i), target_mtrrs->mtrr_var[i].physbase); in x86_pat_sync_task()
181 write_msr(IA32_MTRR_PHYSMASK(i), target_mtrrs->mtrr_var[i].physmask); in x86_pat_sync_task()
203 write_msr(X86_MSR_IA32_PAT, pat_val); in x86_pat_sync_task()
206 write_msr(X86_MSR_IA32_MTRR_DEF_TYPE, target_mtrrs->mtrr_def); in x86_pat_sync_task()
A Dtsc.cpp17 write_msr(X86_MSR_IA32_TSC_ADJUST, tsc_adj); in x86_tsc_adjust()
A Dpvclock.cpp32 write_msr(kKvmBootTime, pa); in pvclock_init()
40 write_msr(kKvmSystemTimeMsr, pa | kSystemTimeEnable); in pvclock_init()
A Dlapic.cpp104 write_msr(LAPIC_X2APIC_MSR_BASE + (uint32_t)(offset >> 4), val); in lapic_reg_write()
158 write_msr(X86_MSR_IA32_APIC_BASE, v); in apic_local_init()
217 write_msr(LAPIC_X2APIC_MSR_ICR, X2_ICR_DST(dst_apic_id) | request); in apic_send_ipi()
234 write_msr(LAPIC_X2APIC_MSR_SELF_IPI, vector); in apic_send_self_ipi()
252 write_msr(LAPIC_X2APIC_MSR_ICR, X2_ICR_BROADCAST | request); in apic_send_broadcast_self_ipi()
271 write_msr(LAPIC_X2APIC_MSR_ICR, X2_ICR_BROADCAST | request); in apic_send_broadcast_ipi()
349 write_msr(X86_MSR_IA32_TSC_DEADLINE, 0); in apic_timer_stop()
393 write_msr(X86_MSR_IA32_TSC_DEADLINE, deadline); in apic_timer_set_tsc_deadline()
A Dmp.cpp145 write_msr(X86_MSR_IA32_KERNEL_GS_BASE, 0); in x86_init_percpu()
183 write_msr(X86_MSR_IA32_LSTAR, (uint64_t)&x86_syscall); in x86_init_percpu()
194 …write_msr(X86_MSR_IA32_STAR, (uint64_t)USER_CODE_SELECTOR << 48 | (uint64_t)CODE_64_SELECTOR << 32… in x86_init_percpu()
205 write_msr(X86_MSR_IA32_FMASK, mask); in x86_init_percpu()
216 write_msr(X86_MSR_IA32_EFER, efer_msr); in x86_init_percpu()
236 write_msr(0x1fc, power_ctl_msr & ~0x2); in x86_init_percpu()
A Dthread.cpp133 write_msr(X86_MSR_IA32_GS_BASE, gs_base); in arch_context_switch()
156 write_msr(X86_MSR_IA32_FS_BASE, newthread->arch.fs_base); in arch_context_switch()
157 write_msr(X86_MSR_IA32_KERNEL_GS_BASE, newthread->arch.gs_base); in arch_context_switch()
A Darch.cpp85 write_msr(X86_MSR_IA32_FS_BASE, 0); in arch_enter_uspace()
88 write_msr(X86_MSR_IA32_KERNEL_GS_BASE, 0); in arch_enter_uspace()
185 write_msr(X86_MSR_IA32_GS_BASE, (uintptr_t)percpu); in x86_secondary_entry()
A Dperf_mon.cpp590 write_msr(IA32_PERF_GLOBAL_OVF_CTRL, value); in x86_perfmon_clear_overflow_indicators()
1586 write_msr(IA32_PERFEVTSEL_FIRST + i, 0); in x86_perfmon_start_cpu_task()
1592 write_msr(IA32_DEBUGCTL, state->debug_ctrl); in x86_perfmon_start_cpu_task()
1744 write_msr(IA32_PERF_GLOBAL_CTRL, 0); in x86_perfmon_stop_cpu_task()
1802 write_msr(IA32_PERF_GLOBAL_CTRL, 0); in x86_perfmon_reset_task()
1806 write_msr(IA32_DEBUGCTL, 0); in x86_perfmon_reset_task()
1810 write_msr(IA32_PMC_FIRST + i, 0); in x86_perfmon_reset_task()
1813 write_msr(IA32_FIXED_CTR_CTRL, 0); in x86_perfmon_reset_task()
1815 write_msr(IA32_FIXED_CTR0 + i, 0); in x86_perfmon_reset_task()
2099 write_msr(IA32_PERF_GLOBAL_CTRL, 0); in apic_pmi_interrupt_handler()
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A Dregisters.cpp677 write_msr(IA32_XSS_MSR, xss); in x86_set_extended_register_pt_state()
A Dmmu.cpp699 write_msr(X86_MSR_IA32_EFER, efer_msr); in x86_mmu_percpu_init()
/kernel/target/pc/multiboot/
A Dpaging.c49 static void write_msr(uint32_t msr, uint64_t value) { in write_msr() function
127 write_msr(X86_MSR_IA32_EFER, read_msr(X86_MSR_IA32_EFER) | X86_EFER_LME); in enable_64bit_paging()
/kernel/syscalls/
A Dsystem_x86.cpp149 write_msr(X86_MSR_PKG_POWER_LIMIT, v); in x86_set_pkg_pl1()
A Dobject.cpp749 write_msr(X86_MSR_IA32_FS_BASE, addr); in sys_object_set_property()
766 write_msr(X86_MSR_IA32_KERNEL_GS_BASE, addr); in sys_object_set_property()
/kernel/arch/x86/hypervisor/
A Dvmx_cpu_state.cpp124 write_msr(X86_MSR_IA32_FEATURE_CONTROL, feature_control); in vmxon_task()
/kernel/arch/x86/include/arch/
A Dx86.h341 static inline void write_msr(uint32_t msr_id, uint64_t msr_write_val) { in write_msr() function

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