Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 5 of 5) sorted by relevance
| /system/dev/display/vim-display/ |
| A D | hdmitx_clk.cpp | 89 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 19); in configure_od3_div()
90 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
114 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 18); in configure_od3_div()
116 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 18); in configure_od3_div()
117 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 2, 16); in configure_od3_div()
118 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
119 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 14, 0); in configure_od3_div()
121 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, shift_sel, 2, 16); in configure_od3_div()
122 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 15); in configure_od3_div()
124 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
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| A D | vpu.h | 33 #define HHI_VID_PLL_CLK_DIV (0x68 << 2) macro
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| /system/dev/display/astro-display/ |
| A D | hhi-regs.h | 17 #define HHI_VID_PLL_CLK_DIV (0x068 << 2) macro
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| A D | astro-clock.cpp | 211 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 19, 1); in Enable()
212 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 15, 1); in Enable()
214 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 18, 1); // Undocumented register bit in Enable()
217 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 19, 1); // Undocumented register bit in Enable()
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| /system/dev/lib/amlogic/include/soc/aml-s912/ |
| A D | s912-hw.h | 157 #define HHI_VID_PLL_CLK_DIV (0x68 << 2) macro
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