1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #define HI_CSI_PHY_CNTL0 0x4C 8 #define HI_CSI_PHY_CNTL1 0x50 9 #define HI_CSI_PHY_CNTL2 0x54 10 #define HI_CSI_PHY_CNTL3 0x58 11 12 #define MIPI_PHY_CTRL 0x00 13 #define MIPI_PHY_CLK_LANE_CTRL 0x04 14 #define MIPI_PHY_DATA_LANE_CTRL 0x08 15 #define MIPI_PHY_DATA_LANE_CTRL1 0x0C 16 #define MIPI_PHY_TCLK_MISS 0x10 17 #define MIPI_PHY_TCLK_SETTLE 0x14 18 #define MIPI_PHY_THS_EXIT 0x18 19 #define MIPI_PHY_THS_SKIP 0x1C 20 #define MIPI_PHY_THS_SETTLE 0x20 21 #define MIPI_PHY_TINIT 0x24 22 #define MIPI_PHY_TULPS_C 0x28 23 #define MIPI_PHY_TULPS_S 0x2C 24 #define MIPI_PHY_TMBIAS 0x30 25 #define MIPI_PHY_TLP_EN_W 0x34 26 #define MIPI_PHY_TLPOK 0x38 27 #define MIPI_PHY_TWD_INIT 0x3C 28 #define MIPI_PHY_TWD_HS 0x40 29 #define MIPI_PHY_AN_CTRL0 0x44 30 #define MIPI_PHY_AN_CTRL1 0x48 31 #define MIPI_PHY_AN_CTRL2 0x4C 32 #define MIPI_PHY_CLK_LANE_STS 0x50 33 #define MIPI_PHY_DATA_LANE0_STS 0x54 34 #define MIPI_PHY_DATA_LANE1_STS 0x58 35 #define MIPI_PHY_DATA_LANE2_STS 0x5C 36 #define MIPI_PHY_DATA_LANE3_STS 0x60 37 #define MIPI_PHY_INT_STS 0x6C 38 #define MIPI_PHY_MUX_CTRL0 0x184 39 #define MIPI_PHY_MUX_CTRL1 0x188 40 41 #define MIPI_CSI_VERSION 0x000 42 #define MIPI_CSI_N_LANES 0x004 43 #define MIPI_CSI_PHY_SHUTDOWNZ 0x008 44 #define MIPI_CSI_DPHY_RSTZ 0x00C 45 #define MIPI_CSI_CSI2_RESETN 0x010 46 #define MIPI_CSI_PHY_STAT 0x014 47 #define MIPI_CSI_DATA_IDS_1 0x018 48 #define MIPI_CSI_DATA_IDS_2 0x01C 49 50 #define FRONTEND_BASE 0x00004800 51 52 #define CSI2_CLK_RESET 0x00 53 #define CSI2_GEN_CTRL0 0x04 54 #define CSI2_GEN_CTRL1 0x08 55 #define CSI2_X_START_END_ISP 0x0C 56 #define CSI2_Y_START_END_ISP 0x10 57 #define CSI2_X_START_END_MEM 0x14 58 #define CSI2_Y_START_END_MEM 0x18 59 #define CSI2_VC_MODE 0x1C 60 #define CSI2_VC_MODE2_MATCH_MASK_L 0x20 61 #define CSI2_VC_MODE2_MATCH_MASK_H 0x24 62 #define CSI2_VC_MODE2_MATCH_TO_VC_L 0x28 63 #define CSI2_VC_MODE2_MATCH_TO_VC_H 0x2C 64 #define CSI2_VC_MODE2_MATCH_TO_IGNORE_L 0x30 65 #define CSI2_VC_MODE2_MATCH_TO_IGNORE_H 0x34 66 #define CSI2_DDR_START_PIX 0x38 67 #define CSI2_DDR_START_PIX_ALT 0x3C 68 #define CSI2_DDR_STRIDE_PIX 0x40 69 #define CSI2_DDR_START_OTHER 0x44 70 #define CSI2_DDR_START_OTHER_ALT 0x48 71 #define CSI2_DDR_MAX_BYTES_OTHER 0x4C 72 #define CSI2_INTERRUPT_CTRL_STAT 0x50 73 74 #define CSI2_GEN_STAT0 0x80 75 #define CSI2_ERR_STAT0 0x84 76 #define CSI2_PIC_SIZE_STAT 0x88 77 #define CSI2_DDR_WPTR_STAT_PIX 0x8C 78 #define CSI2_DDR_WPTR_STAT_OTHER 0x90 79 #define CSI2_STAT_MEM_0 0x94 80 #define CSI2_STAT_MEM_1 0x98 81 82 #define CSI2_STAT_GEN_SHORT_08 0xA0 83 #define CSI2_STAT_GEN_SHORT_09 0xA4 84 #define CSI2_STAT_GEN_SHORT_0A 0xA8 85 #define CSI2_STAT_GEN_SHORT_0B 0xAC 86 #define CSI2_STAT_GEN_SHORT_0C 0xB0 87 #define CSI2_STAT_GEN_SHORT_0D 0xB4 88 #define CSI2_STAT_GEN_SHORT_0E 0xB8 89 #define CSI2_STAT_GEN_SHORT_0F 0xBC 90 91 #define RD_BASE 0x00005000 92 #define MIPI_ADAPT_DDR_RD0_CNTL0 0x00 93 #define MIPI_ADAPT_DDR_RD0_CNTL1 0x04 94 #define MIPI_ADAPT_DDR_RD0_CNTL2 0x08 95 #define MIPI_ADAPT_DDR_RD0_CNTL3 0x0C 96 #define MIPI_ADAPT_DDR_RD1_CNTL0 0x40 97 #define MIPI_ADAPT_DDR_RD1_CNTL1 0x44 98 #define MIPI_ADAPT_DDR_RD1_CNTL2 0x48 99 #define MIPI_ADAPT_DDR_RD1_CNTL3 0x4C 100 101 #define PIXEL_BASE 0x00005000 102 #define MIPI_ADAPT_PIXEL0_CNTL0 0x80 103 #define MIPI_ADAPT_PIXEL0_CNTL1 0x84 104 #define MIPI_ADAPT_PIXEL1_CNTL0 0x88 105 #define MIPI_ADAPT_PIXEL1_CNTL1 0x8C 106 107 108 #define ALIGN_BASE 0x00005000 109 #define MIPI_ADAPT_ALIG_CNTL0 0xC0 110 #define MIPI_ADAPT_ALIG_CNTL1 0xC4 111 #define MIPI_ADAPT_ALIG_CNTL2 0xC8 112 #define MIPI_ADAPT_ALIG_CNTL6 0xD8 113 #define MIPI_ADAPT_ALIG_CNTL7 0xDC 114 #define MIPI_ADAPT_ALIG_CNTL8 0xE0 115 #define MIPI_OTHER_CNTL0 0x100 116 #define MIPI_ADAPT_IRQ_MASK0 0x180 117 #define MIPI_ADAPT_IRQ_PENDING0 0x184 118 119 #define MISC_BASE 0x00005000 120 121 // CLK offsets. 122 #define HHI_MIPI_ISP_CLK_CNTL (0x70 << 2) 123 #define HHI_MIPI_CSI_PHY_CLK_CNTL (0xD0 << 2) 124 #define HHI_CSI_PHY_CNTL0 (0xD3 << 2) 125 #define HHI_CSI_PHY_CNTL1 (0x114 << 2) 126 127 // Power domain. 128 #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) 129 #define AO_RTI_GEN_PWR_ISO0 (0x3b << 2) 130 131 // Memory PD. 132 #define HHI_ISP_MEM_PD_REG0 (0x45 << 2) 133 #define HHI_ISP_MEM_PD_REG1 (0x46 << 2) 134 135 // Reset 136 #define RESET4_LEVEL 0x90 137