1 // Copyright 2017 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD_style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 // MMIO regions 8 #define MMIO_CCI_CFG_BASE 0xE8100000 9 #define MMIO_CCI_CFG_LENGTH 0x100000 10 #define MMIO_GIC400_BASE 0xE82B0000 11 #define MMIO_GIC400_LENGTH 0x8000 12 #define MMIO_HKADC_SSI_BASE 0xE82B8000 13 #define MMIO_HKADC_SSI_LENGTH 0x1000 14 #define MMIO_CODEC_SSI_BASE 0xE82B9000 15 #define MMIO_CODEC_SSI_LENGTH 0x1000 16 #define MMIO_G3D_BASE 0xE82C0000 17 #define MMIO_G3D_LENGTH 0x4000 18 #define MMIO_DSI_BASE 0xE8601000 19 #define MMIO_DSI_LENGTH 0x7F000 20 #define MMIO_IPC_BASE 0xE896A000 21 #define MMIO_IPC_LENGTH 0x1000 22 #define MMIO_IPC_NS_BASE 0xE896B000 23 #define MMIO_IPC_NS_LENGTH 0x1000 24 #define MMIO_IOC_BASE 0xE896C000 25 #define MMIO_IOC_LENGTH 0x1000 26 #define MMIO_TIMER9_BASE 0xE8A00000 27 #define MMIO_TIMER9_LENGTH 0x1000 28 #define MMIO_TIMER10_BASE 0xE8A01000 29 #define MMIO_TIMER10_LENGTH 0x1000 30 #define MMIO_TIMER11_BASE 0xE8A02000 31 #define MMIO_TIMER11_LENGTH 0x1000 32 #define MMIO_TIMER12_BASE 0xE8A03000 33 #define MMIO_TIMER12_LENGTH 0x1000 34 #define MMIO_PWM_BASE 0xE8A04000 35 #define MMIO_PWM_LENGTH 0x1000 36 #define MMIO_WD0_BASE 0xE8A06000 37 #define MMIO_WD0_LENGTH 0x1000 38 #define MMIO_WD1_BASE 0xE8A07000 39 #define MMIO_WD1_LENGTH 0x1000 40 #define MMIO_PCTRL_BASE 0xE8A09000 41 #define MMIO_PCTRL_LENGTH 0x1000 42 #define MMIO_GPIO0_SE_BASE 0xE8A0A000 43 #define MMIO_GPIO0_SE_LENGTH 0x1000 44 #define MMIO_GPIO0_BASE 0xE8A0B000 45 #define MMIO_GPIO0_LENGTH 0x1000 46 #define MMIO_GPIO1_BASE 0xE8A0C000 47 #define MMIO_GPIO1_LENGTH 0x1000 48 #define MMIO_GPIO2_BASE 0xE8A0D000 49 #define MMIO_GPIO2_LENGTH 0x1000 50 #define MMIO_GPIO3_BASE 0xE8A0E000 51 #define MMIO_GPIO3_LENGTH 0x1000 52 #define MMIO_GPIO4_BASE 0xE8A0F000 53 #define MMIO_GPIO4_LENGTH 0x1000 54 #define MMIO_GPIO5_BASE 0xE8A10000 55 #define MMIO_GPIO5_LENGTH 0x1000 56 #define MMIO_GPIO6_BASE 0xE8A11000 57 #define MMIO_GPIO6_LENGTH 0x1000 58 #define MMIO_GPIO7_BASE 0xE8A12000 59 #define MMIO_GPIO7_LENGTH 0x1000 60 #define MMIO_GPIO8_BASE 0xE8A13000 61 #define MMIO_GPIO8_LENGTH 0x1000 62 #define MMIO_GPIO9_BASE 0xE8A14000 63 #define MMIO_GPIO9_LENGTH 0x1000 64 #define MMIO_GPIO10_BASE 0xE8A15000 65 #define MMIO_GPIO10_LENGTH 0x1000 66 #define MMIO_GPIO11_BASE 0xE8A16000 67 #define MMIO_GPIO11_LENGTH 0x1000 68 #define MMIO_GPIO12_BASE 0xE8A17000 69 #define MMIO_GPIO12_LENGTH 0x1000 70 #define MMIO_GPIO13_BASE 0xE8A18000 71 #define MMIO_GPIO13_LENGTH 0x1000 72 #define MMIO_GPIO14_BASE 0xE8A19000 73 #define MMIO_GPIO14_LENGTH 0x1000 74 #define MMIO_GPIO15_BASE 0xE8A1A000 75 #define MMIO_GPIO15_LENGTH 0x1000 76 #define MMIO_GPIO16_BASE 0xE8A1B000 77 #define MMIO_GPIO16_LENGTH 0x1000 78 #define MMIO_GPIO17_BASE 0xE8A1C000 79 #define MMIO_GPIO17_LENGTH 0x1000 80 #define MMIO_GPIO20_BASE 0xE8A1F000 81 #define MMIO_GPIO20_LENGTH 0x1000 82 #define MMIO_GPIO21_BASE 0xE8A20000 83 #define MMIO_GPIO21_LENGTH 0x1000 84 #define MMIO_CFGBUS_SERVICE_TARGET_BASE 0xE9800000 85 #define MMIO_CFGBUS_SERVICE_TARGET_LENGTH 0x10000 86 #define MMIO_UFSBUS_SERVICE_TARGET_BASE 0xE9810000 87 #define MMIO_UFSBUS_SERVICE_TARGET_LENGTH 0x10000 88 #define MMIO_DMA_NOC_SERVICE_TARGET_BASE 0xE9860000 89 #define MMIO_DMA_NOC_SERVICE_TARGET_LENGTH 0x10000 90 #define MMIO_AOBUS_SERVICE_TARGET_BASE 0xE9870000 91 #define MMIO_AOBUS_SERVICE_TARGET_LENGTH 0x10000 92 #define MMIO_MMC1_NOC_SERVICE_TARGET_BASE 0xE9880000 93 #define MMIO_MMC1_NOC_SERVICE_TARGET_LENGTH 0x10000 94 #define MMIO_MMC0_NOC_SERVICE_TARGET_BASE 0xE9890000 95 #define MMIO_MMC0_NOC_SERVICE_TARGET_LENGTH 0x10000 96 #define MMIO_CSSYS_APB_BASE 0xEC000000 97 #define MMIO_CSSYS_APB_LENGTH 0x1800000 98 #define MMIO_IOMCU_TCM_BASE 0xF0000000 99 #define MMIO_IOMCU_TCM_LENGTH 0xC00000 100 #define MMIO_PCIEPHY_BASE 0xF3F00000 101 #define MMIO_PCIEPHY_LENGTH 0x40000 102 #define MMIO_PCIECTRL_BASE 0xF4000000 103 #define MMIO_PCIECTRL_LENGTH 0x8000000 104 #define MMIO_UART1_BASE 0xFDF00000 105 #define MMIO_UART1_LENGTH 0x1000 106 #define MMIO_UART4_BASE 0xFDF01000 107 #define MMIO_UART4_LENGTH 0x1000 108 #define MMIO_UART0_BASE 0xFDF02000 109 #define MMIO_UART0_LENGTH 0x1000 110 #define MMIO_UART2_BASE 0xFDF03000 111 #define MMIO_UART2_LENGTH 0x1000 112 #define MMIO_UART5_BASE 0xFDF05000 113 #define MMIO_UART5_LENGTH 0x1000 114 #define MMIO_SPI4_BASE 0xFDF06000 115 #define MMIO_SPI4_LENGTH 0x1000 116 #define MMIO_SPI1_BASE 0xFDF08000 117 #define MMIO_SPI1_LENGTH 0x1000 118 #define MMIO_I2C7_BASE 0xFDF0B000 119 #define MMIO_I2C7_LENGTH 0x1000 120 #define MMIO_I2C3_BASE 0xFDF0C000 121 #define MMIO_I2C3_LENGTH 0x1000 122 #define MMIO_I2C4_BASE 0xFDF0D000 123 #define MMIO_I2C4_LENGTH 0x1000 124 #define MMIO_PERF_STAT_BASE 0xFDF10000 125 #define MMIO_PERF_STAT_LENGTH 0x1000 126 #define MMIO_PERI_DMAC_BASE 0xFDF30000 127 #define MMIO_PERI_DMAC_LENGTH 0x1000 128 #define MMIO_IPC_MDM_S_BASE 0xFF010000 129 #define MMIO_IPC_MDM_S_LENGTH 0x1000 130 #define MMIO_IPC_MDM_NS_BASE 0xFF011000 131 #define MMIO_IPC_MDM_NS_LENGTH 0x1000 132 #define MMIO_USB3OTG_BASE 0xFF100000 133 #define MMIO_USB3OTG_LENGTH 0x100000 134 #define MMIO_USB3OTG_BC_BASE 0xFF200000 135 #define MMIO_USB3OTG_BC_LENGTH 0x1000 136 #define MMIO_IOC_MMC0_BASE 0xFF37E000 137 #define MMIO_IOC_MMC0_LENGTH 0x1000 138 #define MMIO_SD3_BASE 0xFF37F000 139 #define MMIO_SD3_LENGTH 0x1000 140 #define MMIO_UFS_CFG_BASE 0xFF3B0000 141 #define MMIO_UFS_CFG_LENGTH 0x1000 142 #define MMIO_UFS_SYS_CTRL_BASE 0xFF3B1000 143 #define MMIO_UFS_SYS_CTRL_LENGTH 0x1000 144 #define MMIO_SPI3_BASE 0xFF3B3000 145 #define MMIO_SPI3_LENGTH 0x1000 146 #define MMIO_GPIO18_BASE 0xFF3B4000 147 #define MMIO_GPIO18_LENGTH 0x1000 148 #define MMIO_GPIO19_BASE 0xFF3B5000 149 #define MMIO_GPIO19_LENGTH 0x1000 150 #define MMIO_IOC_FIX_BASE 0xFF3B6000 151 #define MMIO_IOC_FIX_LENGTH 0x1000 152 #define MMIO_GPIO0_MMC1_BASE 0xFF3E0000 153 #define MMIO_GPIO0_MMC1_LENGTH 0x1000 154 #define MMIO_GPIO1_MMC1_BASE 0xFF3E1000 155 #define MMIO_GPIO1_MMC1_LENGTH 0x1000 156 #define MMIO_EMMC_BASE 0xFF3FB000 157 #define MMIO_EMMC_LENGTH 0x1000 158 #define MMIO_IOC_MMC1_BASE 0xFF3FD000 159 #define MMIO_IOC_MMC1_LENGTH 0x1000 160 #define MMIO_PCIE_APB_CFG_BASE 0xFF3FE000 161 #define MMIO_PCIE_APB_CFG_LENGTH 0x1000 162 #define MMIO_SDIO0_BASE 0xFF3FF000 163 #define MMIO_SDIO0_LENGTH 0x1000 164 #define MMIO_IOMCU_BASE 0xFFD00000 165 #define MMIO_IOMCU_LENGTH 0x80000 166 #define MMIO_I2C0_BASE 0xFFD71000 167 #define MMIO_I2C0_LENGTH 0x1000 168 #define MMIO_I2C1_BASE 0xFFD72000 169 #define MMIO_I2C1_LENGTH 0x1000 170 #define MMIO_I2C2_BASE 0xFFD73000 171 #define MMIO_I2C2_LENGTH 0x1000 172 #define MMIO_IOMCU_CONFIG_BASE 0xFFD7E000 173 #define MMIO_IOMCU_CONFIG_LENGTH 0x1000 174 #define MMIO_RTC0_BASE 0xFFF04000 175 #define MMIO_RTC0_LENGTH 0x1000 176 #define MMIO_RTC1_BASE 0xFFF05000 177 #define MMIO_RTC1_LENGTH 0x1000 178 #define MMIO_SYS_CNT_BASE 0xFFF08000 179 #define MMIO_SYS_CNT_LENGTH 0x2000 180 #define MMIO_SCTRL_BASE 0xFFF0A000 181 #define MMIO_SCTRL_LENGTH 0x1000 182 #define MMIO_GPIO22_BASE 0xFFF0B000 183 #define MMIO_GPIO22_LENGTH 0x1000 184 #define MMIO_GPIO23_BASE 0xFFF0C000 185 #define MMIO_GPIO23_LENGTH 0x1000 186 #define MMIO_GPIO24_BASE 0xFFF0D000 187 #define MMIO_GPIO24_LENGTH 0x1000 188 #define MMIO_GPIO25_BASE 0xFFF0E000 189 #define MMIO_GPIO25_LENGTH 0x1000 190 #define MMIO_GPIO26_BASE 0xFFF0F000 191 #define MMIO_GPIO26_LENGTH 0x1000 192 #define MMIO_GPIO27_BASE 0xFFF10000 193 #define MMIO_GPIO27_LENGTH 0x1000 194 #define MMIO_AO_IOC_BASE 0xFFF11000 195 #define MMIO_AO_IOC_LENGTH 0x1000 196 #define MMIO_IOMG_PMX4_BASE 0xFFF11000 197 #define MMIO_IOMG_PMX4_LENGTH 0x1000 198 #define MMIO_TIMER0_BASE 0xFFF14000 199 #define MMIO_TIMER0_LENGTH 0x1000 200 #define MMIO_TIMER1_BASE 0xFFF15000 201 #define MMIO_TIMER1_LENGTH 0x1000 202 #define MMIO_TIMER2_BASE 0xFFF16000 203 #define MMIO_TIMER2_LENGTH 0x1000 204 #define MMIO_TIMER3_BASE 0xFFF17000 205 #define MMIO_TIMER3_LENGTH 0x1000 206 #define MMIO_TIMER4_BASE 0xFFF18000 207 #define MMIO_TIMER4_LENGTH 0x1000 208 #define MMIO_TIMER5_BASE 0xFFF19000 209 #define MMIO_TIMER5_LENGTH 0x1000 210 #define MMIO_TIMER6_BASE 0xFFF1A000 211 #define MMIO_TIMER6_LENGTH 0x1000 212 #define MMIO_TIMER7_BASE 0xFFF1B000 213 #define MMIO_TIMER7_LENGTH 0x1000 214 #define MMIO_TIMER8_BASE 0xFFF1C000 215 #define MMIO_TIMER8_LENGTH 0x1000 216 #define MMIO_GPIO28_BASE 0xFFF1D000 217 #define MMIO_GPIO28_LENGTH 0x1000 218 #define MMIO_TSENSORC_BASE 0xFFF30000 219 #define MMIO_TSENSORC_LENGTH 0x1000 220 #define MMIO_PMCTRL_BASE 0xFFF31000 221 #define MMIO_PMCTRL_LENGTH 0x1000 222 #define MMIO_UART6_BASE 0xFFF32000 223 #define MMIO_UART6_LENGTH 0x1000 224 #define MMIO_PMU_I2C_BASE 0xFFF33000 225 #define MMIO_PMU_I2C_LENGTH 0x1000 226 #define MMIO_PMU_SSI0_BASE 0xFFF34000 227 #define MMIO_PMU_SSI0_LENGTH 0x1000 228 #define MMIO_PERI_CRG_BASE 0xFFF35000 229 #define MMIO_PERI_CRG_LENGTH 0x1000 230 #define MMIO_PMU_SSI1_BASE 0xFFF36000 231 #define MMIO_PMU_SSI1_LENGTH 0x1000 232 #define MMIO_PMU_SSI2_BASE 0xFFF38000 233 #define MMIO_PMU_SSI2_LENGTH 0x1000 234 235 // Interrupts 236 #define IRQ_A73_INTERR 32 237 #define IRQ_A73_EXTERR 33 238 #define IRQ_A73_PMU0 34 239 #define IRQ_A73_PMU1 35 240 #define IRQ_A73_PMU2 36 241 #define IRQ_A73_PMU3 37 242 #define IRQ_A73_CTI0 38 243 #define IRQ_A73_CTI1 39 244 #define IRQ_A73_CTI2 40 245 #define IRQ_A73_CTI3 41 246 #define IRQ_A73_COMMRX0 42 247 #define IRQ_A73_COMMRX1 43 248 #define IRQ_A73_COMMRX2 44 249 #define IRQ_A73_COMMRX3 45 250 #define IRQ_A73_COMMTX0 46 251 #define IRQ_A73_COMMTX1 47 252 #define IRQ_A73_COMMTX2 48 253 #define IRQ_A73_COMMTX3 49 254 #define IRQ_A73_COMMIRQ0 50 255 #define IRQ_A73_COMMIRQ1 51 256 #define IRQ_A73_COMMIRQ2 52 257 #define IRQ_A73_COMMIRQ3 53 258 #define IRQ_A53_INTERR 54 259 #define IRQ_A53_EXTERR 55 260 #define IRQ_A53_PMU0 56 261 #define IRQ_A53_PMU1 57 262 #define IRQ_A53_PMU2 58 263 #define IRQ_A53_PMU3 59 264 #define IRQ_A53_CTI0 60 265 #define IRQ_A53_CTI1 61 266 #define IRQ_A53_CTI2 62 267 #define IRQ_A53_CTI3 63 268 #define IRQ_A53_COMMRX0 64 269 #define IRQ_A53_COMMRX1 65 270 #define IRQ_A53_COMMRX2 66 271 #define IRQ_A53_COMMRX3 67 272 #define IRQ_A53_COMMTX0 68 273 #define IRQ_A53_COMMTX1 69 274 #define IRQ_A53_COMMTX2 70 275 #define IRQ_A53_COMMTX3 71 276 #define IRQ_A53_COMMIRQ0 72 277 #define IRQ_A53_COMMIRQ1 73 278 #define IRQ_A53_COMMIRQ2 74 279 #define IRQ_A53_COMMIRQ3 75 280 #define IRQ_WATCHDOG0 76 281 #define IRQ_WATCHDOG1 77 282 #define IRQ_RTC0 78 283 #define IRQ_RTC1 79 284 #define IRQ_TIME00 80 285 #define IRQ_TIME01 81 286 #define IRQ_TIME10 82 287 #define IRQ_TIME11 83 288 #define IRQ_TIME20 84 289 #define IRQ_TIME21 85 290 #define IRQ_TIME30 86 291 #define IRQ_TIME31 87 292 #define IRQ_TIME40 88 293 #define IRQ_TIME41 89 294 #define IRQ_TIME50 90 295 #define IRQ_TIME51 91 296 #define IRQ_TIME60 92 297 #define IRQ_TIME61 93 298 #define IRQ_TIME70 94 299 #define IRQ_TIME71 95 300 #define IRQ_TIME80 96 301 #define IRQ_TIME81 97 302 #define IRQ_TIME90 98 303 #define IRQ_TIME91 99 304 #define IRQ_TIME100 100 305 #define IRQ_TIME101 101 306 #define IRQ_TIME110 102 307 #define IRQ_TIME111 103 308 #define IRQ_TIME120 104 309 #define IRQ_TIME121 105 310 #define IRQ_UART0 106 311 #define IRQ_UART1 107 312 #define IRQ_UART2 108 313 #define IRQ_UART4 109 314 #define IRQ_UART5 110 315 #define IRQ_UART6 111 316 #define IRQ_SPI1 112 317 #define IRQ_I2C3 113 318 #define IRQ_I2C4 114 319 #define IRQ_I2C5 115 320 #define IRQ_GPIO0_INTR1 116 321 #define IRQ_GPIO1_INTR1 117 322 #define IRQ_GPIO2_INTR1 118 323 #define IRQ_GPIO3_INTR1 119 324 #define IRQ_GPIO4_INTR1 120 325 #define IRQ_GPIO5_INTR1 121 326 #define IRQ_GPIO6_INTR1 122 327 #define IRQ_GPIO7_INTR1 123 328 #define IRQ_GPIO8_INTR1 124 329 #define IRQ_GPIO9_INTR1 125 330 #define IRQ_GPIO10_INTR1 126 331 #define IRQ_GPIO11_INTR1 127 332 #define IRQ_GPIO12_INTR1 128 333 #define IRQ_GPIO13_INTR1 129 334 #define IRQ_GPIO14_INTR1 130 335 #define IRQ_GPIO15_INTR1 131 336 #define IRQ_GPIO16_INTR1 132 337 #define IRQ_GPIO17_INTR1 133 338 #define IRQ_GPIO18_INTR1 134 339 #define IRQ_GPIO19_INTR1 135 340 #define IRQ_GPIO20_INTR1 136 341 #define IRQ_GPIO21_INTR1 137 342 #define IRQ_GPIO22_INTR1 138 343 #define IRQ_GPIO23_INTR1 139 344 #define IRQ_GPIO24_INTR1 140 345 #define IRQ_GPIO25_INTR1 141 346 #define IRQ_GPIO26_INTR1 142 347 #define IRQ_GPIO27_INTR1 143 348 #define IRQ_IOMCU_WD 144 349 #define IRQ_IOMCU_SPI 145 350 #define IRQ_IOMCU_UART3 146 351 #define IRQ_IOMCU_UART8 147 352 #define IRQ_IOMCU_SPI2 148 353 #define IRQ_IOMCU_I2C3 149 354 #define IRQ_IOMCU_I2C0 150 355 #define IRQ_IOMCU_I2C1 151 356 #define IRQ_IOMCU_I2C2 152 357 #define IRQ_IOMCU_GPIO0_INT1 153 358 #define IRQ_IOMCU_GPIO1_INT1 154 359 #define IRQ_IOMCU_GPIO2_INT1 155 360 #define IRQ_IOMCU_GPIO3_INT1 156 361 #define IRQ_IOMCU_DMAC_INT0 157 362 #define IRQ_IOMCU_DMAC_NS_INT0 158 363 #define IRQ_PERF_STAT 159 364 #define IRQ_IOMCU_COMB 160 365 #define IRQ_IOMCU_BLPWM 161 366 #define IRQ_NOC_COMB 162 367 #define IRQ_INTR_DMSS 163 368 #define IRQ_INTR_DDRC0_ERR 164 369 #define IRQ_INTR_DDRC1_ERR 165 370 #define IRQ_PMCTRL 166 371 #define IRQ_SECENG_P 167 372 #define IRQ_SECENG_S 168 373 #define IRQ_EMMC51 169 374 #define IRQ_ASP_IPC_MODEM_CBBE 170 375 #define IRQ_SD3 171 376 #define IRQ_SDIO 172 377 #define IRQ_GPIO28_INTR1 173 378 #define IRQ_PERI_DMAC_INT0 174 379 #define IRQ_PERI_DMAC_NS_INT0 175 380 #define IRQ_CLK_MONITOR 176 381 #define IRQ_TSENSOR_A73 177 382 #define IRQ_TSENSOR_A53 178 383 #define IRQ_TSENSOR_G3D 179 384 #define IRQ_TSENSOR_MODEM 180 385 #define IRQ_ASP_ARM_SECURE 181 386 #define IRQ_ASP_ARM 182 387 #define IRQ_VDM_INT2 183 388 #define IRQ_VDM_INT0 184 389 #define IRQ_VDM_INT1 185 390 #define IRQ_MODEM_IPC0 186 391 #define IRQ_MODEM_IPC1 187 392 #define IRQ_MDM_BUS_ERR 188 393 #define IRQ_MDM_EDMAC0_INTR_NS_0 190 394 #define IRQ_USB3 191 395 #define IRQ_USB3_OTG 193 396 #define IRQ_USB3_BC 194 397 #define IRQ_GPIO1_SE_INTR1 195 398 #define IRQ_GPIO0_SE_INTR1 196 399 #define IRQ_PMC_DVFS_A73 197 400 #define IRQ_PMC_DVFS_A53 198 401 #define IRQ_PMC_DVFS_G3D 199 402 #define IRQ_PMC_AVS_A73 200 403 #define IRQ_PMC_AVS_A53 201 404 #define IRQ_PMC_AVS_G3D 202 405 #define IRQ_PMC_AVS_IDLE_A73 203 406 #define IRQ_PMC_AVS_IDLE_A53 204 407 #define IRQ_PMC_AVS_IDLE_G3D 205 408 #define IRQ_M3_LP_WD 206 409 #define IRQ_CCI400_ERR 207 410 #define IRQ_CCI400_OVERFLOW_6_0 208 411 #define IRQ_CCI400_OVERFLOW_7 209 412 #define IRQ_IPC_S_INT0 210 413 #define IRQ_IPC_S_INT1 211 414 #define IRQ_IPC_S_INT4 212 415 #define IRQ_IPC_S_MBX0 213 416 #define IRQ_IPC_S_MBX1 214 417 #define IRQ_IPC_S_MBX2 215 418 #define IRQ_IPC_S_MBX3 216 419 #define IRQ_IPC_S_MBX4 217 420 #define IRQ_IPC_S_MBX5 218 421 #define IRQ_IPC_S_MBX6 219 422 #define IRQ_IPC_S_MBX7 220 423 #define IRQ_IPC_S_MBX8 221 424 #define IRQ_IPC_S_MBX9 222 425 #define IRQ_IPC_S_MBX18 223 426 #define IRQ_IPC_NS_INT0 224 427 #define IRQ_IPC_NS_INT1 225 428 #define IRQ_IPC_NS_INT4 226 429 #define IRQ_IPC_NS_INT5 227 430 #define IRQ_IPC_NS_INT6 228 431 #define IRQ_IPC_NS_MBX0 229 432 #define IRQ_IPC_NS_MBX1 230 433 #define IRQ_IPC_NS_MBX2 231 434 #define IRQ_IPC_NS_MBX3 232 435 #define IRQ_IPC_NS_MBX4 233 436 #define IRQ_IPC_NS_MBX5 234 437 #define IRQ_IPC_NS_MBX6 235 438 #define IRQ_IPC_NS_MBX7 236 439 #define IRQ_IPC_NS_MBX8 237 440 #define IRQ_IPC_NS_MBX9 238 441 #define IRQ_IPC_NS_MBX18 239 442 #define IRQ_MDM_AXIMON_INTR 240 443 #define IRQ_MDM_WDOG_INTR 241 444 #define IRQ_ASP_IPC_ARM 242 445 #define IRQ_ASP_IPC_MCPU 243 446 #define IRQ_ASP_IPC_BBE16 244 447 #define IRQ_ASP_WD 245 448 #define IRQ_ASP_AXI_DLOCK 246 449 #define IRQ_ASP_DMA_SECURE 247 450 #define IRQ_ASP_DMA_SECURE_N 248 451 #define IRQ_SCI0 249 452 #define IRQ_SCI1 250 453 #define IRQ_SOCP0 251 454 #define IRQ_SOCP1 252 455 #define IRQ_MDM_IPF_INTR0 253 456 #define IRQ_MDM_IPF_INTR1 254 457 #define IRQ_IDDRC_FATAL_INT_3_0 255 458 #define IRQ_MDM_AXI_DLOCK_INT 256 459 #define IRQ_MDM_WDT1_INTR 257 460 #define IRQ_GIC_IRQ_OUT_0 258 461 #define IRQ_GIC_IRQ_OUT_1 259 462 #define IRQ_GIC_IRQ_OUT_2 260 463 #define IRQ_GIC_IRQ_OUT_3 261 464 #define IRQ_GIC_IRQ_OUT_4 262 465 #define IRQ_GIC_IRQ_OUT_5 263 466 #define IRQ_GIC_IRQ_OUT_6 264 467 #define IRQ_GIC_IRQ_OUT_7 265 468 #define IRQ_GIC_FIQ_OUT_0 266 469 #define IRQ_GIC_FIQ_OUT_1 267 470 #define IRQ_GIC_FIQ_OUT_2 268 471 #define IRQ_GIC_FIQ_OUT_3 269 472 #define IRQ_GIC_FIQ_OUT_4 270 473 #define IRQ_GIC_FIQ_OUT_5 271 474 #define IRQ_GIC_FIQ_OUT_6 272 475 #define IRQ_GIC_FIQ_OUT_7 273 476 #define IRQ_NANDC 274 477 #define IRQ_CORESIGHT_ETR_FULL 275 478 #define IRQ_CORESIGHT_ETF_FULL 276 479 #define IRQ_DSS_PDP 277 480 #define IRQ_DSS_SDP 278 481 #define IRQ_DSS_OFFLINE 279 482 #define IRQ_DSS_MCU_PDP 280 483 #define IRQ_DSS_MCU_SDP 281 484 #define IRQ_DSS_MCU_OFFLINE 282 485 #define IRQ_DSS_DSI0 283 486 #define IRQ_DSS_DSI1 284 487 #define IRQ_IVP32_SMMU_IRPT_S 285 488 #define IRQ_IVP32_SMMU_IRPT_NS 286 489 #define IRQ_IVP32_WATCH_DOG 287 490 #define IRQ_ATGC 288 491 #define IRQ_G3D_IRQEVENT 289 492 #define IRQ_G3D_JOB 290 493 #define IRQ_G3D_MMU 291 494 #define IRQ_G3D_GPU 292 495 #define IRQ_ISP_IRQ_0 293 496 #define IRQ_ISP_IRQ_1 294 497 #define IRQ_ISP_IRQ_2 295 498 #define IRQ_ISP_IRQ_3 296 499 #define IRQ_ISP_IRQ_4 297 500 #define IRQ_ISP_IRQ_5 298 501 #define IRQ_ISP_IRQ_6 299 502 #define IRQ_ISP_IRQ_7 300 503 #define IRQ_ISP_A7_TO_GIC_MBX_INT_0 301 504 #define IRQ_ISP_A7_TO_GIC_MBX_INT_1 302 505 #define IRQ_ISP_A7_TO_GIC_IPC_INT 303 506 #define IRQ_ISP_A7_WATCHDOG_INT 304 507 #define IRQ_ISP_AXI_DLCOK 305 508 #define IRQ_ISP_A7_IRQ_OUT 306 509 #define IRQ_IVP32_DWAXI_DLOCK_IRQ 307 510 #define IRQ_MMBUF_ASC0 308 511 #define IRQ_MMBUF_ASC1 309 512 #define IRQ_UFS 310 513 #define IRQ_PCIE_LINK_DOWN_INT 311 514 #define IRQ_PCIE_EDMA_INT 312 515 #define IRQ_PCIE_PM_INT 313 516 #define IRQ_PCIE_RADM_INTA 314 517 #define IRQ_PCIE_RADM_INTB 315 518 #define IRQ_PCIE_RADM_INTC 316 519 #define IRQ_PCIE_RADM_INTD 317 520 #define IRQ_PSAM_INTR_0 318 521 #define IRQ_PSAM_INTR_1 319 522 #define IRQ_OCBC_PE_NPINT_0 320 523 #define IRQ_INTR_WDOG_OCBC 321 524 #define IRQ_INTR_VDEC_MFDE_NORM 322 525 #define IRQ_INTR_VDEC_SCD_NORM 323 526 #define IRQ_INTR_VDEC_BPD_NORM 324 527 #define IRQ_INTR_VDEC_MMU_NORM 325 528 #define IRQ_INTR_VDEC_MFDE_SAFE 326 529 #define IRQ_INTR_VDEC_SCD_SAFE 327 530 #define IRQ_INTR_VDEC_BPD_SAFE 328 531 #define IRQ_INTR_VDEC_MMU_SAFE 329 532 #define IRQ_INTR_VENC_VEDU_NORM 330 533 #define IRQ_INTR_VENC_MMU_NORM 331 534 #define IRQ_INTR_VENC_VEDU_SAFE 332 535 #define IRQ_INTR_VENC_MMU_SAFE 333 536 #define IRQ_INTR_QOSBUF0 334 537 #define IRQ_INTR_QOSBUF1 335 538 #define IRQ_INTR_DDRC2_ERR 336 539 #define IRQ_INTR_DDRC3_ERR 337 540 #define IRQ_INTR_DDRPHY_0 338 541 #define IRQ_INTR_DDRPHY_1 339 542 #define IRQ_INTR_DDRPHY_2 340 543 #define IRQ_INTR_DDRPHY_3 341 544 #define IRQ_INTR0_MDM_IPC_GIC_S 342 545 #define IRQ_INTR1_MDM_IPC_GIC_S 343 546 #define IRQ_SPI3 344 547 #define IRQ_SPI4 345 548 #define IRQ_I2C7 346 549 #define IRQ_INTR_UCE0_WDOG 347 550 #define IRQ_INTR_UCE1_WDOG 348 551 #define IRQ_INTR_UCE2_WDOG 349 552 #define IRQ_INTR_UCE3_WDOG 350 553 #define IRQ_INTR_EXMBIST 351 554 #define IRQ_INTR_HISEE_WDOG 352 555 #define IRQ_INTR_HISEE_IPC_MBX_GIC_0 353 556 #define IRQ_INTR_HISEE_IPC_MBX_GIC_1 354 557 #define IRQ_INTR_HISEE_IPC_MBX_GIC_2 355 558 #define IRQ_INTR_HISEE_IPC_MBX_GIC_3 356 559 #define IRQ_INTR_HISEE_IPC_MBX_GIC_4 357 560 #define IRQ_INTR_HISEE_IPC_MBX_GIC_5 358 561 #define IRQ_INTR_HISEE_IPC_MBX_GIC_6 359 562 #define IRQ_INTR_HISEE_IPC_MBX_GIC_7 360 563 #define IRQ_INTR_HISEE_ALARM_0 361 564 #define IRQ_INTR_HISEE_ALARM_1 362 565 #define IRQ_INTR_HISEE_EH2H_SLV 365 566 #define IRQ_INTR_HISEE_AS2AP_IRQ 366 567 #define IRQ_INTR_HISEE_DS2AP_IRQ 367 568 #define IRQ_INTR_HISEE_SENC2AP_IRQ 368 569 #define IRQ_GPIO0_EMMC 369 570 #define IRQ_GPIO1_EMMC 370 571 #define IRQ_AONOC_TIMEOUT 371 572 #define IRQ_INTR_HISEE_TSENSOR_0 372 573 #define IRQ_INTR_HISEE_TSENSOR_1 373 574 #define IRQ_INTR_HISEE_LOCKUP 374 575 #define IRQ_INTR_HISEE_DMA 375 576 577 // I2C ports 578 enum { 579 DW_I2C_0, 580 DW_I2C_1, 581 DW_I2C_2, 582 DW_I2C_COUNT, 583 }; 584 585 typedef enum hisi_3660_sep_gate_clk_idx { 586 HI3660_PERI_VOLT_HOLD = 0, 587 HI3660_HCLK_GATE_SDIO0, 588 HI3660_HCLK_GATE_SD, 589 HI3660_CLK_GATE_AOMM, 590 HI3660_PCLK_GPIO0, 591 HI3660_PCLK_GPIO1, 592 HI3660_PCLK_GPIO2, 593 HI3660_PCLK_GPIO3, 594 HI3660_PCLK_GPIO4, 595 HI3660_PCLK_GPIO5, 596 HI3660_PCLK_GPIO6, 597 HI3660_PCLK_GPIO7, 598 HI3660_PCLK_GPIO8, 599 HI3660_PCLK_GPIO9, 600 HI3660_PCLK_GPIO10, 601 HI3660_PCLK_GPIO11, 602 HI3660_PCLK_GPIO12, 603 HI3660_PCLK_GPIO13, 604 HI3660_PCLK_GPIO14, 605 HI3660_PCLK_GPIO15, 606 HI3660_PCLK_GPIO16, 607 HI3660_PCLK_GPIO17, 608 HI3660_PCLK_GPIO18, 609 HI3660_PCLK_GPIO19, 610 HI3660_PCLK_GPIO20, 611 HI3660_PCLK_GPIO21, 612 HI3660_CLK_GATE_SPI3, 613 HI3660_CLK_GATE_I2C7, 614 HI3660_CLK_GATE_I2C3, 615 HI3660_CLK_GATE_SPI1, 616 HI3660_CLK_GATE_UART1, 617 HI3660_CLK_GATE_UART2, 618 HI3660_CLK_GATE_UART4, 619 HI3660_CLK_GATE_UART5, 620 HI3660_CLK_GATE_I2C4, 621 HI3660_CLK_GATE_DMAC, 622 HI3660_CLK_GATE_VENC, 623 HI3660_CLK_GATE_VDEC, 624 HI3660_PCLK_GATE_DSS, 625 HI3660_ACLK_GATE_DSS, 626 HI3660_CLK_GATE_LDI1, 627 HI3660_CLK_GATE_LDI0, 628 HI3660_CLK_GATE_VIVOBUS, 629 HI3660_CLK_GATE_EDC0, 630 HI3660_CLK_GATE_TXDPHY0_CFG, 631 HI3660_CLK_GATE_TXDPHY0_REF, 632 HI3660_CLK_GATE_TXDPHY1_CFG, 633 HI3660_CLK_GATE_TXDPHY1_REF, 634 HI3660_ACLK_GATE_USB3OTG, 635 HI3660_CLK_GATE_SPI4, 636 HI3660_CLK_GATE_SD, 637 HI3660_CLK_GATE_SDIO0, 638 HI3660_CLK_GATE_ISP_SNCLK0, 639 HI3660_CLK_GATE_ISP_SNCLK1, 640 HI3660_CLK_GATE_ISP_SNCLK2, 641 HI3660_CLK_GATE_UFS_SUBSYS, 642 HI3660_PCLK_GATE_DSI0, 643 HI3660_PCLK_GATE_DSI1, 644 HI3660_ACLK_GATE_PCIE, 645 HI3660_PCLK_GATE_PCIE_SYS, 646 HI3660_CLK_GATE_PCIEAUX, 647 HI3660_PCLK_GATE_PCIE_PHY, 648 649 HI3660_PCLK_MMBUF_ANDGT, 650 HI3660_CLK_MMBUF_PLL_ANDGT, 651 HI3660_CLK_FLL_MMBUF_ANDGT, 652 HI3660_CLK_SYS_MMBUF_ANDGT, 653 HI3660_CLK_GATE_PCIEPHY_GT, 654 655 // Must be last. 656 HI3660_SEP_CLK_GATE_COUNT, 657 } hisi_3660_sep_gate_clk_idx_t;