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Searched refs:READ32_REG (Results 1 – 8 of 8) sorted by relevance

/system/dev/display/astro-display/
A Daml-dsi-host.cpp257 DISP_INFO("DW_DSI_VERSION = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_VERSION)); in Dump()
258 DISP_INFO("DW_DSI_PWR_UP = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_PWR_UP)); in Dump()
267 READ32_REG(MIPI_DSI, DW_DSI_DBI_PARTITIONING_EN)); in Dump()
294 DISP_INFO("DW_DSI_SDF_3D = 0x%x\n", READ32_REG(MIPI_DSI, DW_DSI_SDF_3D)); in Dump()
314 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SUSPEND_CNTL)); in Dump()
316 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_SUSPEND_LINE)); in Dump()
321 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_TE0)); in Dump()
323 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_TE1)); in Dump()
325 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_VS0)); in Dump()
327 READ32_REG(MIPI_DSI, MIPI_DSI_TOP_MEAS_STAT_VS1)); in Dump()
[all …]
A Dosd.cpp441 uint32_t regVal = READ32_REG(VPU, VPP_OFIFO_SIZE); in HwInit()
495 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
497 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
499 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
501 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
504 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
506 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
508 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
510 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
512 DISP_INFO("reg[0x%x]: 0x%08x\n", reg, READ32_REG(VPU, reg)); in Dump()
[all …]
A Daml-mipi-phy.cpp293 DISP_INFO("MIPI_DSI_PHY_CTRL = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_PHY_CTRL)); in Dump()
294 DISP_INFO("MIPI_DSI_CHAN_CTRL = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL)); in Dump()
295 DISP_INFO("MIPI_DSI_CHAN_STS = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_CHAN_STS)); in Dump()
296 DISP_INFO("MIPI_DSI_CLK_TIM = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_CLK_TIM)); in Dump()
297 DISP_INFO("MIPI_DSI_HS_TIM = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_HS_TIM)); in Dump()
298 DISP_INFO("MIPI_DSI_LP_TIM = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_LP_TIM)); in Dump()
300 DISP_INFO("MIPI_DSI_INIT_TIM = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_INIT_TIM)); in Dump()
302 DISP_INFO("MIPI_DSI_LPOK_TIM = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_LPOK_TIM)); in Dump()
303 DISP_INFO("MIPI_DSI_LP_WCHDOG = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_LP_WCHDOG)); in Dump()
304 DISP_INFO("MIPI_DSI_ANA_CTRL = 0x%x\n", READ32_REG(DSI_PHY, MIPI_DSI_ANA_CTRL)); in Dump()
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A Dcommon.h27 #define READ32_REG(x, a) READ32_##x##_REG(a) macro
A Ddw-mipi-dsi.cpp94 *data = READ32_REG(MIPI_DSI, DW_DSI_GEN_PLD_DATA); in GenericPayloadRead()
A Dastro-clock.cpp341 WRITE32_REG(VPU, VPP_MISC, READ32_REG(VPU, VPP_MISC) & ~(VPP_OUT_SATURATE)); in Enable()
/system/dev/display/vim-display/
A Dhdmitx.cpp853 regval = (READ32_REG(VPU, VPU_HDMI_SETTING) & 0xf00) >> 8; in init_hdmi_interface()
887 reg_val = READ32_REG(HHI, ladr); in dump_regs()
893 reg_val = READ32_REG(VPU, ladr); in dump_regs()
898 reg_val = READ32_REG(VPU, ladr); in dump_regs()
903 reg_val = READ32_REG(VPU, ladr); in dump_regs()
A Dhdmitx.h51 #define READ32_REG(x, a) READ32_##x##_REG(a) macro

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