1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #define S905D2_GPIOZ_COUNT 16 8 #define S905D2_GPIOA_COUNT 16 9 #define S905D2_GPIOBOOT_COUNT 16 10 #define S905D2_GPIOC_COUNT 8 11 #define S905D2_GPIOX_COUNT 20 12 #define S905D2_GPIOH_COUNT 9 13 #define S905D2_GPIOAO_COUNT 12 14 #define S905D2_GPIOE_COUNT 3 15 16 #define S905D2_GPIOZ_START 0 17 #define S905D2_GPIOA_START S905D2_GPIOZ_COUNT 18 #define S905D2_GPIOBOOT_START (S905D2_GPIOA_START + S905D2_GPIOA_COUNT) 19 #define S905D2_GPIOC_START (S905D2_GPIOBOOT_START + S905D2_GPIOBOOT_COUNT) 20 #define S905D2_GPIOX_START (S905D2_GPIOC_START + S905D2_GPIOC_COUNT) 21 #define S905D2_GPIOH_START (S905D2_GPIOX_START + S905D2_GPIOX_COUNT) 22 #define S905D2_GPIOAO_START (S905D2_GPIOH_START + S905D2_GPIOH_COUNT) 23 #define S905D2_GPIOE_START (S905D2_GPIOAO_START + S905D2_GPIOAO_COUNT) 24 25 #define S905D2_GPIOZ(n) (S905D2_GPIOZ_START + n) 26 #define S905D2_GPIOA(n) (S905D2_GPIOA_START + n) 27 #define S905D2_GPIOBOOT(n) (S905D2_GPIOBOOT_START + n) 28 #define S905D2_GPIOC(n) (S905D2_GPIOC_START + n) 29 #define S905D2_GPIOX(n) (S905D2_GPIOX_START + n) 30 #define S905D2_GPIOH(n) (S905D2_GPIOH_START + n) 31 #define S905D2_GPIOAO(n) (S905D2_GPIOAO_START + n) 32 // GPIOE is contained in GPIO AO bank 33 #define S905D2_GPIOE(n) (S905D2_GPIOE_START + n) 34 35 #define S905D2_PREG_PAD_GPIO0_EN_N 0x10 36 #define S905D2_PREG_PAD_GPIO0_O 0x11 37 #define S905D2_PREG_PAD_GPIO0_I 0x12 38 #define S905D2_PREG_PAD_GPIO1_EN_N 0x13 39 #define S905D2_PREG_PAD_GPIO1_O 0x14 40 #define S905D2_PREG_PAD_GPIO1_I 0x15 41 #define S905D2_PREG_PAD_GPIO2_EN_N 0x16 42 #define S905D2_PREG_PAD_GPIO2_O 0x17 43 #define S905D2_PREG_PAD_GPIO2_I 0x18 44 #define S905D2_PREG_PAD_GPIO3_EN_N 0x19 45 #define S905D2_PREG_PAD_GPIO3_O 0x1a 46 #define S905D2_PREG_PAD_GPIO3_I 0x1b 47 #define S905D2_PREG_PAD_GPIO4_EN_N 0x1c 48 #define S905D2_PREG_PAD_GPIO4_O 0x1d 49 #define S905D2_PREG_PAD_GPIO4_I 0x1e 50 #define S905D2_PREG_PAD_GPIO5_EN_N 0x20 51 #define S905D2_PREG_PAD_GPIO5_O 0x21 52 #define S905D2_PREG_PAD_GPIO5_I 0x22 53 54 #define S905D2_PAD_PULL_UP_EN_REG0 0x48 55 #define S905D2_PAD_PULL_UP_EN_REG1 0x49 56 #define S905D2_PAD_PULL_UP_EN_REG2 0x4a 57 #define S905D2_PAD_PULL_UP_EN_REG3 0x4b 58 #define S905D2_PAD_PULL_UP_EN_REG4 0x4c 59 #define S905D2_PAD_PULL_UP_EN_REG5 0x4d 60 61 #define S905D2_PULL_UP_REG0 0x3a 62 #define S905D2_PULL_UP_REG1 0x3b 63 #define S905D2_PULL_UP_REG2 0x3c 64 #define S905D2_PULL_UP_REG3 0x3d 65 #define S905D2_PULL_UP_REG4 0x3e 66 #define S905D2_PULL_UP_REG5 0x3f 67 68 #define S905D2_AO_PAD_DS_A 0x07 69 #define S905D2_AO_PAD_DS_B 0x08 70 #define S905D2_PAD_DS_REG1A 0xd1 71 #define S905D2_PAD_DS_REG2A 0xd2 72 #define S905D2_PAD_DS_REG2B 0xd3 73 #define S905D2_PAD_DS_REG3A 0xd4 74 #define S905D2_PAD_DS_REG4A 0xd5 75 #define S905D2_PAD_DS_REG5A 0xd6 76 77 #define S905D2_PERIPHS_PIN_MUX_0 0xb0 78 #define S905D2_PERIPHS_PIN_MUX_1 0xb1 79 #define S905D2_PERIPHS_PIN_MUX_2 0xb2 80 #define S905D2_PERIPHS_PIN_MUX_3 0xb3 81 #define S905D2_PERIPHS_PIN_MUX_4 0xb4 82 #define S905D2_PERIPHS_PIN_MUX_5 0xb5 83 #define S905D2_PERIPHS_PIN_MUX_6 0xb6 84 #define S905D2_PERIPHS_PIN_MUX_7 0xb7 85 #define S905D2_PERIPHS_PIN_MUX_9 0xb9 86 #define S905D2_PERIPHS_PIN_MUX_B 0xbb 87 #define S905D2_PERIPHS_PIN_MUX_C 0xbc 88 #define S905D2_PERIPHS_PIN_MUX_D 0xbd 89 #define S905D2_PERIPHS_PIN_MUX_E 0xbe 90 91 #define S905D2_AO_GPIO_O_EN_N 0x09 92 #define S905D2_AO_GPIO_I 0x0a 93 #define S905D2_AO_GPIO_O 0x0d 94 95 #define S905D2_GPIOAO_PULL_UP_REG 0x0b 96 #define S905D2_GPIOAO_PULL_EN_REG 0x0c 97 98 #define S905D2_AO_RTI_PINMUX_REG0 0x05 99 #define S905D2_AO_RTI_PINMUX_REG1 0x06 100 101 // These are relative to base address 0xffd00000 and in sizeof(uint32_t) 102 #define S905D2_GPIO_INT_EDGE_POLARITY 0x3c20 103 #define S905D2_GPIO_0_3_PIN_SELECT 0x3c21 104 #define S905D2_GPIO_4_7_PIN_SELECT 0x3c22 105 #define S905D2_GPIO_FILTER_SELECT 0x3c23 106 107 #define S905D2_GPIOA0_PIN_START 0 108 #define S905D2_GPIOZ_PIN_START 12 109 #define S905D2_GPIOH_PIN_START 28 110 #define S905D2_GPIOBOOT_PIN_START 37 111 #define S905D2_GPIOC_PIN_START 53 112 #define S905D2_GPIOA_PIN_START 61 113 #define S905D2_GPIOX_PIN_START 77 114 #define S905D2_GPIOE_PIN_START 97 115 116 //GPIOA pin alternate functions 117 #define S905D2_GPIOA_1_TDMB_SCLK_FN 1 118 #define S905D2_GPIOA_1_TDMB_SLV_SCLK_FN 2 119 #define S905D2_GPIOA_2_TDMB_FS_FN 1 120 #define S905D2_GPIOA_2_TDMB_SLV_FS_FN 2 121 #define S905D2_GPIOA_3_TDMB_D0_FN 1 122 #define S905D2_GPIOA_3_TDMB_DIN0_FN 2 123 #define S905D2_GPIOA_6_PDM_DIN2_FN 1 124 #define S905D2_GPIOA_6_TDMB_DIN3_FN 2 125 #define S905D2_GPIOA_6_TDMB_D3_FN 3 126 #define S905D2_GPIOA_7_PDM_DCLK_FN 1 127 #define S905D2_GPIOA_7_TDMC_D3_FN 2 128 #define S905D2_GPIOA_7_TDMC_DIN3_FN 3 129 #define S905D2_GPIOA_8_PDM_DIN0_FN 1 130 #define S905D2_GPIOA_8_TDMC_D2_FN 2 131 #define S905D2_GPIOA_8_TDMC_DIN2_FN 3 132 #define S905D2_GPIOA_9_PDM_DIN1_FN 1 133 #define S905D2_GPIOA_9_TDMC_D1_FN 2 134 #define S905D2_GPIOA_9_TDMC_DIN1_FN 3 135 136 #define S905D2_GPIOZ_2_TDMC_D0_FN 4 137 #define S905D2_GPIOZ_3_TDMC_D1_FN 4 138 #define S905D2_GPIOZ_4_TDMC_D2_FN 4 139 #define S905D2_GPIOZ_5_TDMC_D3_FN 4 140 #define S905D2_GPIOZ_6_TDMC_FS_FN 4 141 #define S905D2_GPIOZ_7_TDMC_SCLK_FN 4 142 143 #define S905D2_GPIOAO_9_MCLK_FN 5 144