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Searched refs:SET_BIT32 (Results 1 – 10 of 10) sorted by relevance

/system/dev/display/vim-display/
A Dhdmitx_clk.cpp37 SET_BIT32(HHI, reg, 1, 1, 28); \
38 SET_BIT32(HHI, reg, 0, 1, 28); \
72 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x1, 1, 28); in configure_hpll_clk_out()
73 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x0, 1, 28); in configure_hpll_clk_out()
89 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 19); in configure_od3_div()
90 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); in configure_od3_div()
127 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 19); in configure_od3_div()
135 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 3, 9); in configure_pll()
136 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 7, 0); in configure_pll()
137 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 1, 1, 8); in configure_pll()
[all …]
A Dhdmitx.cpp91 SET_BIT32(CBUS, PAD_PULL_UP_EN_REG1, 0, 2, 21); in init_hdmi_hardware()
92 SET_BIT32(CBUS, PAD_PULL_UP_REG1, 0, 2, 21); in init_hdmi_hardware()
94 SET_BIT32(CBUS, PERIPHS_PIN_MUX_6, 3, 2, 29); in init_hdmi_hardware()
100 SET_BIT32(HHI, HHI_GCLK_MPEG2, 1, 1, 4); in init_hdmi_hardware()
103 SET_BIT32(HHI, HHI_MEM_PD_REG0, 0, 8, 8); in init_hdmi_hardware()
117 SET_BIT32(HDMITX, 0x8, 1, 1, 15); in init_hdmi_hardware()
118 SET_BIT32(HDMITX, 0x18, 1, 1, 15); in init_hdmi_hardware()
460 SET_BIT32(VPU, VPU_HDMI_SETTING, 2, 2, 0); in hdmi_config_encoder()
847 SET_BIT32(VPU, VPU_HDMI_FMT_CTRL, 0, 1, 4); in init_hdmi_interface()
848 SET_BIT32(VPU, VPU_HDMI_FMT_CTRL, 1, 1, 10); in init_hdmi_interface()
[all …]
A Dhdmitx.h46 #define SET_BIT32(x, dest, value, count, start) \ macro
/system/dev/display/astro-display/
A Dvpu.cpp118 SET_BIT32(VPU, VPP_OFIFO_SIZE, 0xFFF, 0, 12); in VppInit()
121 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0x7, 12, 3); in VppInit()
216 SET_BIT32(VPU, VPP_MATRIX_CTRL, 1, 0, 1); in VppInit()
217 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0, 8, 3); in VppInit()
234 SET_BIT32(VPU, VPP_MATRIX_CLIP, 0, 5, 3); in VppInit()
241 SET_BIT32(HHI, HHI_VPU_CLK_CNTL, 1, 8, 1); in ConfigureClock()
251 SET_BIT32(HHI, HHI_VAPBCLK_CNTL, 1, 8, 1); in ConfigureClock()
253 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 0, 0, 8); in ConfigureClock()
275 SET_BIT32(HHI, HHI_VPU_MEM_PD_REG2, 0, 0, 2); in PowerOn()
348 SET_BIT32(HHI, HHI_VAPBCLK_CNTL, 0, 8, 1); in PowerOff()
[all …]
A Dastro-clock.cpp57 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL3, 1, 31, 1); in PllLockWait()
152 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, 0, 5); in Disable()
153 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); in Disable()
207 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); in Enable()
211 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 19, 1); in Enable()
212 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 15, 1); in Enable()
220 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 0, 21, 3); in Enable()
221 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 0, 12, 7); in Enable()
222 SET_BIT32(HHI, HHI_VDIN_MEAS_CLK_CNTL, 1, 20, 1); in Enable()
227 SET_BIT32(HHI, HHI_MIPIDSI_PHY_CLK_CNTL, 1, 8, 1); in Enable()
[all …]
A Daml-dsi-host.cpp32 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_DPI_FORMAT, in HostModeInit()
34 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_VENC_DATA_WIDTH, in HostModeInit()
36 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0, in HostModeInit()
158 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0x3, 4, 2); in HostOn()
160 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0xf, 0, 4); in HostOn()
162 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0x0, 0, 4); in HostOn()
164 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CLK_CNTL, 0x3, 0, 2); in HostOn()
188 SET_BIT32(MIPI_DSI, DW_DSI_LPCLK_CTRL, 1, LPCLK_CTRL_AUTOCLKLANE_CTRL, 1); in HostOn()
A Dosd.cpp239 SET_BIT32(VPU, DOLBY_PATH_CTRL, 0x3, 2, 2); in DefaultSetup()
260 SET_BIT32(VPU, VPU_VIU_OSD1_CTRL_STAT, kHwOsdBlockEnable0, 0, 4); in DefaultSetup()
331 SET_BIT32(VPU,VPU_VPP_OSD_HSC_PHASE_STEP, in EnableScaling()
333 SET_BIT32(VPU,VPU_VPP_OSD_HSC_INI_PHASE, 0, 0, 16); in EnableScaling()
334 SET_BIT32(VPU,VPU_VPP_OSD_VSC_PHASE_STEP, in EnableScaling()
471 SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0000, 0, 9); in HwInit()
476 SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0100, 0, 9); in HwInit()
A Daml-mipi-phy.cpp138 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 1, PHY_CTRL_RST_START, PHY_CTRL_RST_BITS); in PhyInit()
139 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 0, PHY_CTRL_RST_START, PHY_CTRL_RST_BITS); in PhyInit()
206 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 0, 7, 1); in Shutdown()
245 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 1, 1, 1); in Startup()
A Ddw-mipi-dsi.cpp120 SET_BIT32(MIPI_DSI, DW_DSI_CMD_MODE_CFG, in EnableBta()
123 SET_BIT32(MIPI_DSI, DW_DSI_PCKHDL_CFG, in EnableBta()
129 SET_BIT32(MIPI_DSI, DW_DSI_CMD_MODE_CFG, in DisableBta()
132 SET_BIT32(MIPI_DSI, DW_DSI_PCKHDL_CFG, in DisableBta()
A Dcommon.h13 #define SET_BIT32(x, dest, value, start, count) \ macro

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