1 // Copyright 2016 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 // PERI_CRG registers 8 #define PERI_CRG_CLK_EN4 0x40 9 10 #define PERI_CRG_RSTEN4 0x90 11 #define PERI_CRG_RSTDIS4 0x94 12 #define PERI_CRG_ISODIS 0x148 13 14 #define PERI_CRG_GT_CLK_USB3OTG_REF (1 << 0) 15 #define PERI_CRG_GT_ACLK_USB3OTG (1 << 1) 16 17 #define PERI_CRG_IP_RST_USB3OTGPHY_POR (1 << 3) 18 #define PERI_CRG_IP_RST_USB3OTG (1 << 5) 19 #define PERI_CRG_IP_RST_USB3OTG_32K (1 << 6) 20 #define PERI_CRG_IP_RST_USB3OTG_AHBIF (1 << 7) 21 #define PERI_CRG_IP_RST_USB3OTG_MUX (1 << 8) 22 #define PERI_CRG_ISODIS_REFCLK_ISO_EN (1 << 25) 23 24 // PCTRL registers 25 #define PCTRL_CTRL3 0x10 26 #define PCTRL_CTRL24 0x064 27 28 #define PCTRL_CTRL3_USB_TCXO_EN (1 << 1) 29 #define PCTRL_CTRL3_MSK_START 16 30 #define PCTRL_CTRL24_SC_CLK_USB3PHY_3MUX1_SEL (1 << 25) 31 32 // USBOTG_BC registers 33 #define USB3OTG_CTRL0 0x00 34 #define USB3OTG_CTRL1 0x04 35 #define USB3OTG_CTRL2 0x08 36 #define USB3OTG_CTRL3 0x0C 37 #define USB3OTG_CTRL4 0x10 38 #define USB3OTG_CTRL5 0x14 39 #define USB3OTG_CTRL6 0x18 40 #define USB3OTG_CTRL7 0x1C 41 #define USB3OTG_STS0 0x20 42 #define USB3OTG_STS1 0x24 43 #define USB3OTG_STS2 0x28 44 #define USB3OTG_STS3 0x2C 45 #define BC_CTRL0 0x30 46 #define BC_CTRL1 0x34 47 #define BC_CTRL2 0x38 48 #define BC_STS0 0x3C 49 #define RAM_CTRL 0x40 50 #define USB3OTG_STS4 0x44 51 #define USB3PHY_CTRL 0x48 52 #define USB3PHY_STS 0x4C 53 #define USB3OTG_PHY_CR_STS 0x50 54 #define USB3OTG_PHY_CR_CTRL 0x54 55 #define USB3_RES 0x58 56 57 // USB3OTG_CTRL0 BITS 58 #define USB3OTG_CTRL0_ABB_GT_EN (1 << 15) 59 60 // USB3OTG_CTRL2 bits 61 # define USB3OTG_CTRL2_POWERDOWN_HSP (1 << 0) 62 # define USB3OTG_CTRL2_POWERDOWN_SSP (1 << 1) 63 64 // USB3OTG_CTRL3 bits 65 #define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6) 66 #define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5) 67 68 // USB3OTG_CTRL7 bits 69 #define USB3OTG_CTRL7_REF_SSP_EN (1 << 16) 70 71 // LDO3 Enable Reg 72 #define LDO3_ENABLE_REG (0x60 << 2) 73 #define LDO3_ENABLE_BIT (0x2) 74 75 // DSI0 76 #define PERRSTDIS3 0x088 77 #define TXDPHY0_CFG_OFFSET 0x30 78 #define TXDPHY0_CFG_BIT 28 79 #define TXDPHY0_REF_OFFSET 0x30 80 #define TXDPHY0_REF_BIT 29 81 #define PCLK_GATE_DSI0_OFFSET 0x50 82 #define PCLK_GATE_DSI0_BIT 28 83 84 #define CLKGATE_SEPARATED_ENABLE 0x0 85 #define CLKGATE_SEPARATED_DISABLE 0x4 86 #define CLKGATE_SEPARATED_STATUS 0x8 87