1 // Copyright 2017 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #pragma once
6 
7 // size of phy port register block
8 #define PHY_REGISTER_SIZE 32
9 #define U2P_R0_OFFSET   0
10 #define U2P_R1_OFFSET   4
11 #define U2P_R2_OFFSET   8
12 
13 #define USB_R0_OFFSET   0
14 #define USB_R1_OFFSET   4
15 #define USB_R2_OFFSET   8
16 #define USB_R3_OFFSET   12
17 #define USB_R4_OFFSET   16
18 #define USB_R5_OFFSET   20
19 
20 #define U2P_R0_BYPASS_SEL                       (1 << 0)
21 #define U2P_R0_BYPASS_DM_EN                     (1 << 1)
22 #define U2P_R0_BYPASS_DP_EN                     (1 << 2)
23 #define U2P_R0_TXBITSTUFFENH                    (1 << 3)
24 #define U2P_R0_TXBITSTUFFEN                     (1 << 4)
25 #define U2P_R0_DMPULLDOWN                       (1 << 5)
26 #define U2P_R0_DPPULLDOWN                       (1 << 6)
27 #define U2P_R0_VBUSVLDEXTSEL                    (1 << 7)
28 #define U2P_R0_VBUSVLDEXT                       (1 << 8)
29 #define U2P_R0_ADP_PRB_EN                       (1 << 9)
30 #define U2P_R0_ADP_DISCHRG                      (1 << 10)
31 #define U2P_R0_ADP_CHRG                         (1 << 11)
32 #define U2P_R0_DRVVBUS                          (1 << 12)
33 #define U2P_R0_IDPULLUP                         (1 << 13)
34 #define U2P_R0_LOOPBACKENB                      (1 << 14)
35 #define U2P_R0_OTGDISABLE                       (1 << 15)
36 #define U2P_R0_COMMONONN                        (1 << 16)
37 #define U2P_R0_FSEL_START                       17
38 #define U2P_R0_FSEL_BITS                        3
39 #define U2P_R0_REFCLKSEL_START                  20
40 #define U2P_R0_REFCLKSEL_BITS                   2
41 #define U2P_R0_POR                              (1 << 22)
42 #define U2P_R0_VATESTENB_START                  23
43 #define U2P_R0_VATESTENB_BITS                   2
44 #define U2P_R0_SET_IDDQ                         (1 << 25)
45 #define U2P_R0_ATE_RESET                        (1 << 26)
46 #define U2P_R0_FSV_MINUS                        (1 << 27)
47 #define U2P_R0_FSV_PLUS                         (1 << 28)
48 #define U2P_R0_BYPASS_DM_DATA                   (1 << 29)
49 #define U2P_R0_BYPASS_DP_DATA                   (1 << 30)
50 
51 #define U2P_R1_BURN_IN_TEST                     (1 << 0)
52 #define U2P_R1_ACA_ENABLE                       (1 << 1)
53 #define U2P_R1_DCD_ENABLE                       (1 << 2)
54 #define U2P_R1_VDATSRCENB                       (1 << 3)
55 #define U2P_R1_VDATDETENB                       (1 << 4)
56 #define U2P_R1_CHRGSEL                          (1 << 5)
57 #define U2P_R1_TX_PREEMP_PULSE_TUNE             (1 << 6)
58 #define U2P_R1_TX_PREEMP_AMP_TUNE_START         7
59 #define U2P_R1_TX_PREEMP_AMP_TUNE_BITS          2
60 #define U2P_R1_TX_RES_TUNE_START                9
61 #define U2P_R1_TX_RES_TUNE_BITS                 2
62 #define U2P_R1_TX_RISE_TUNE_START               11
63 #define U2P_R1_TX_RISE_TUNE_BITS                2
64 #define U2P_R1_TX_VREF_TUNE_START               13
65 #define U2P_R1_TX_VREF_TUNE_BITS                4
66 #define U2P_R1_TX_FSLS_TUNE_START               17
67 #define U2P_R1_TX_FSLS_TUNE_BITS                4
68 #define U2P_R1_TX_HSXV_TUNE_START               21
69 #define U2P_R1_TX_HSXV_TUNE_BITS                2
70 #define U2P_R1_OTG_TUNE_START                   23
71 #define U2P_R1_OTG_TUNE_BITS                    3
72 #define U2P_R1_SQRX_TUNE_START                  26
73 #define U2P_R1_SQRX_TUNE_BITS                   3
74 #define U2P_R1_COMP_DIS_TUNE_START              29
75 #define U2P_R1_COMP_DIS_TUNE_BITS               3
76 
77 #define U2P_R2_DATA_IN_START                    0
78 #define U2P_R2_DATA_IN_BITS                     4
79 #define U2P_R2_DATA_IN_EN_START                 4
80 #define U2P_R2_DATA_IN_EN_BITS                  4
81 #define U2P_R2_ADDR_START                       8
82 #define U2P_R2_ADDR_BITS                        4
83 #define U2P_R2_DATA_OUT_SEL                     (1 << 12)
84 #define U2P_R2_CLK                              (1 << 13)
85 #define U2P_R2_DATA_OUT_START                    14
86 #define U2P_R2_DATA_OUT_BITS                     4
87 #define U2P_R2_ACA_PIN_RANGE_C                  (1 << 18)
88 #define U2P_R2_ACA_PIN_RANGE_B                  (1 << 19)
89 #define U2P_R2_ACA_PIN_RANGE_A                  (1 << 20)
90 #define U2P_R2_ACA_PIN_GND                      (1 << 21)
91 #define U2P_R2_ACA_PIN_FLOAT                    (1 << 22)
92 #define U2P_R2_CHG_DET                          (1 << 23)
93 #define U2P_R2_DEVICE_SESS_VLD                  (1 << 24)
94 #define U2P_R2_ADP_PROBE                        (1 << 25)
95 #define U2P_R2_ADP_SENSE                        (1 << 26)
96 #define U2P_R2_SESSEND                          (1 << 27)
97 #define U2P_R2_VBUSVALID                        (1 << 28)
98 #define U2P_R2_BVALID                           (1 << 29)
99 #define U2P_R2_AVALID                           (1 << 30)
100 #define U2P_R2_IDDIG                            (1 << 31)
101 
102 #define USB_R0_P30_FSEL_START                   0
103 #define USB_R0_P30_FSEL_BITS                    6
104 #define USB_R0_P30_PHY_RESET                    (1 << 6)
105 #define USB_R0_P30_TEST_POWERDOWN_HSP           (1 << 7)
106 #define USB_R0_P30_TEST_POWERDOWN_SSP           (1 << 8)
107 #define USB_R0_P30_ACJT_LEVEL_START             9
108 #define USB_R0_P30_ACJT_LEVEL_BITS              5
109 #define USB_R0_P30_TX_VBOOST_LVL_START          14
110 #define USB_R0_P30_TX_VBOOST_LVL_BITS           3
111 #define USB_R0_P30_LANE0_TX2RX_LOOPBK           (1 << 17)
112 #define USB_R0_P30_LANE0_EXT_PCLK_REQ           (1 << 18)
113 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_START    19
114 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_BITS     10
115 #define USB_R0_U2D_SS_SCALEDOWN_MODE_START      29
116 #define USB_R0_U2D_SS_SCALEDOWN_MODE_BITS       2
117 #define USB_R0_U2D_ACT                          (1 << 31)
118 
119 #define USB_R1_U3H_BIGENDIAN_GS                 (1 << 0)
120 #define USB_R1_U3H_PME_EN                       (1 << 1)
121 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_START   2
122 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_BITS    5
123 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_START   7
124 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_BITS    5
125 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_START   12
126 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_BITS    4
127 #define USB_R1_U3H_HOST_U3_PORT_DISABLE         (1 << 16)
128 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT  (1 << 17)
129 #define USB_R1_U3H_HOST_MSI_ENABLE              (1 << 18)
130 #define USB_R1_U3H_FLADJ_30MHZ_REG_START        19
131 #define USB_R1_U3H_FLADJ_30MHZ_REG_BITS         6
132 #define USB_R1_P30_PCS_TX_SWING_FULL_START      25
133 #define USB_R1_P30_PCS_TX_SWING_FULL            7
134 
135 #define USB_R2_P30_CR_DATA_IN_START             0
136 #define USB_R2_P30_CR_DATA_IN_BITS              16
137 #define USB_R2_P30_CR_READ                      (1 << 16)
138 #define USB_R2_P30_CR_WRITE                     (1 << 17)
139 #define USB_R2_P30_CR_CAP_ADDR                  (1 << 18)
140 #define USB_R2_P30_CR_CAP_DATA                  (1 << 19)
141 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_START    20
142 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_BITS     6
143 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_START      26
144 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_BITS       6
145 
146 #define USB_R3_P30_SSC_EN                       (1 << 0)
147 #define USB_R3_P30_SSC_RANGE_START              1
148 #define USB_R3_P30_SSC_RANGE_BITS               3
149 #define USB_R3_P30_SSC_REF_CLK_SEL_START        4
150 #define USB_R3_P30_SSC_REF_CLK_SEL_BITS         9
151 #define USB_R3_P30_REF_SSP_EN                   (1 << 13)
152 #define USB_R3_RESERVED14_START                 14
153 #define USB_R3_RESERVED14_BITS                  2
154 #define USB_R3_P30_LOS_BIAS_START               16
155 #define USB_R3_P30_LOS_BIAS_BITS                3
156 #define USB_R3_P30_LOS_LEVEL_START              19
157 #define USB_R3_P30_LOS_LEVEL_BITS               5
158 #define USB_R3_P30_MPLL_MULTIPLIER_START        24
159 #define USB_R3_P30_MPLL_MULTIPLIER_BITS         7
160 
161 #define USB_R4_P21_PORTRESET0                   (1 << 0)
162 #define USB_R4_P21_SLEEPM0                      (1 << 1)
163 #define USB_R4_MEM_PD_START                     2
164 #define USB_R4_MEM_PD_BITS                      2
165 #define USB_R4_P21_ONLY                         (1 << 4)
166 
167 #define USB_R5_IDDIG_SYNC                       (1 << 0)
168 #define USB_R5_IDDIG_REG                        (1 << 1)
169 #define USB_R5_IDDIG_CFG_START                  2
170 #define USB_R5_IDDIG_CFG_BITS                   2
171 #define USB_R5_IDDIG_EN0                        (1 << 4)
172 #define USB_R5_IDDIG_EN1                        (1 << 5)
173 #define USB_R5_IDDIG_CURR                       (1 << 6)
174 #define USB_R5_IDDIG_IRQ                        (1 << 7)
175 #define USB_R5_IDDIG_TH_START                   8
176 #define USB_R5_IDDIG_TH_BITS                    8
177 #define USB_R5_IDDIG_CNT_START                  16
178 #define USB_R5_IDDIG_CNT_BITS                   8
179 
180 #define USB_R6_P30_CR_DATA_OUT_START            0
181 #define USB_R6_P30_CR_DATA_OUT_BITS             16
182 #define USB_R6_P30_CR_ACK                       (1 << 16)
183