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Searched refs:WRITE32_REG (Results 1 – 10 of 10) sorted by relevance

/system/dev/display/astro-display/
A Dvpu.cpp119 WRITE32_REG(VPU, VPP_HOLD_LINES, 0x08080808); in VppInit()
139 WRITE32_REG(VPU, VPP_WRAP_OSD1_MATRIX_COEF22, in VppInit()
189 WRITE32_REG(VPU, DOLBY_PATH_CTRL, 0xf); in VppInit()
199 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF00_01, in VppInit()
201 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF02_10, in VppInit()
203 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF11_12, in VppInit()
207 WRITE32_REG(VPU, VPP_POST2_MATRIX_COEF22, in VppInit()
211 WRITE32_REG(VPU, VPP_POST2_MATRIX_OFFSET2, in VppInit()
230 WRITE32_REG(VPU, VPP_MATRIX_COEF22, 0x0); in VppInit()
232 WRITE32_REG(VPU, VPP_MATRIX_OFFSET2, 0x0); in VppInit()
[all …]
A Dastro-clock.cpp149 WRITE32_REG(VPU, ENCL_VIDEO_EN, 0); in Disable()
183 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL0, regVal); in Enable()
186 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL2, 0x00); in Enable()
257 WRITE32_REG(VPU, ENCL_VIDEO_EN, 0); in Enable()
267 WRITE32_REG(VPU, ENCL_VIDEO_FILT_CTRL, 0x1000); in Enable()
280 WRITE32_REG(VPU, ENCL_VIDEO_RGBIN_CTRL, 3); in Enable()
281 WRITE32_REG(VPU, ENCL_VIDEO_EN, 1); in Enable()
283 WRITE32_REG(VPU, L_RGB_BASE_ADDR, 0); in Enable()
284 WRITE32_REG(VPU, L_RGB_COEFF_ADDR, 0x400); in Enable()
285 WRITE32_REG(VPU, L_DITH_CNTL_ADDR, 0x400); in Enable()
[all …]
A Daml-dsi-host.cpp40 WRITE32_REG(MIPI_DSI, DW_DSI_DPI_CFG_POL, 0); in HostModeInit()
54 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NUM_CHUNKS, 0); in HostModeInit()
55 WRITE32_REG(MIPI_DSI, DW_DSI_VID_NULL_SIZE, 0); in HostModeInit()
70 WRITE32_REG(MIPI_DSI, DW_DSI_CLKMGR_CFG, in HostModeInit()
75 WRITE32_REG(MIPI_DSI, DW_DSI_MODE_CFG, opp); in HostModeInit()
78 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_LPCLK_CFG, in HostModeInit()
81 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TMR_CFG, in HostModeInit()
100 WRITE32_REG(HHI, HHI_MIPI_CNTL0, 0); in PhyDisable()
101 WRITE32_REG(HHI, HHI_MIPI_CNTL1, 0); in PhyDisable()
102 WRITE32_REG(HHI, HHI_MIPI_CNTL2, 0); in PhyDisable()
[all …]
A Daml-mipi-phy.cpp141 WRITE32_REG(DSI_PHY, MIPI_DSI_CLK_TIM, in PhyInit()
148 WRITE32_REG(DSI_PHY, MIPI_DSI_HS_TIM, in PhyInit()
153 WRITE32_REG(DSI_PHY, MIPI_DSI_LP_TIM, in PhyInit()
165 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0); in PhyInit()
204 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_RST); in Shutdown()
205 WRITE32_REG(DSI_PHY, MIPI_DSI_CHAN_CTRL, 0x1f); in Shutdown()
218 WRITE32_REG(MIPI_DSI, DW_DSI_PWR_UP, PWR_UP_ON); in Startup()
225 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2); in Startup()
226 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x0); in Startup()
228 WRITE32_REG(MIPI_DSI, DW_DSI_PHY_TST_CTRL0, 0x2); in Startup()
[all …]
A Dosd.cpp188 WRITE32_REG(VPU, VIU_OSD_BLEND_CTRL, in DefaultSetup()
199 WRITE32_REG(VPU, OSD1_BLEND_SRC_CTRL, in DefaultSetup()
206 WRITE32_REG(VPU, OSD2_BLEND_SRC_CTRL, in DefaultSetup()
214 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_DATA0, in DefaultSetup()
219 WRITE32_REG(VPU, VIU_OSD_BLEND_DUMMY_ALPHA, in DefaultSetup()
225 WRITE32_REG(VPU, in DefaultSetup()
229 WRITE32_REG(VPU, in DefaultSetup()
241 WRITE32_REG(VPU, VPP_OSD1_IN_SIZE, in DefaultSetup()
245 WRITE32_REG(VPU, VPP_OSD1_BLD_H_SCOPE, in DefaultSetup()
247 WRITE32_REG(VPU, VPP_OSD1_BLD_V_SCOPE, in DefaultSetup()
[all …]
A Dcommon.h26 #define WRITE32_REG(x, a, v) WRITE32_##x##_REG(a, v) macro
A Ddw-mipi-dsi.cpp104 WRITE32_REG(MIPI_DSI, DW_DSI_GEN_HDR, data); in GenericHdrWrite()
114 WRITE32_REG(MIPI_DSI, DW_DSI_GEN_PLD_DATA, data); in GenericPayloadWrite()
/system/dev/display/vim-display/
A Dhdmitx.cpp81 WRITE32_REG(HHI,HHI_HDMI_PHY_CNTL0, 0); in hdmi_shutdown()
82 WRITE32_REG(HHI,HHI_HDMI_PHY_CNTL3, 0); in hdmi_shutdown()
84 WRITE32_REG(HHI,HHI_HDMI_PLL_CNTL, 0); in hdmi_shutdown()
395 WRITE32_REG(VPU, VPU_ENCP_VIDEO_HSO_BEGIN, 0); in hdmi_config_encoder()
409 WRITE32_REG(VPU, VPU_ENCP_DE_H_END, h_end); in hdmi_config_encoder()
450 WRITE32_REG(VPU, VPU_HDMI_SETTING, 0); in hdmi_config_encoder()
717 WRITE32_REG(HHI, HHI_HDMI_PHY_CNTL0, 0); in hdmi_config_phy()
759 WRITE32_REG(VPU, VPU_VENC_VIDEO_TST_EN, 1);
804 WRITE32_REG(HHI, HHI_VDAC_CNTL0, 0); in init_hdmi_interface()
854 WRITE32_REG(VPU, VPU_ENCP_VIDEO_EN, 0); in init_hdmi_interface()
[all …]
A Dhdmitx_clk.cpp62 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL, regVal); in configure_hpll_clk_out()
65 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL1, 0x800cb000); in configure_hpll_clk_out()
68 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL2, 0x860f30c4); in configure_hpll_clk_out()
69 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL3, 0x0c8e0000); in configure_hpll_clk_out()
70 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL4, 0x001fa729); in configure_hpll_clk_out()
71 WRITE32_REG(HHI, HHI_HDMI_PLL_CNTL5, 0x01a31500); in configure_hpll_clk_out()
A Dhdmitx.h50 #define WRITE32_REG(x, a, v) WRITE32_##x##_REG(a, v) macro

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