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Searched refs:bit (Results 1 – 25 of 34) sorted by relevance

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/system/dev/clk/amlogic-clk/
A Daml-gxl-blocks.h17 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 0}, // CLK_GXL_DDR
18 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 1}, // CLK_GXL_DOS
19 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 5}, // CLK_GXL_ISA
20 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 6}, // CLK_GXL_PL301
22 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 8}, // CLK_GXL_SPICC
23 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 9}, // CLK_GXL_I2C
24 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 10}, // CLK_GXL_SANA
26 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 12}, // CLK_GXL_RNG0
28 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 14}, // CLK_GXL_SDHC
31 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 17}, // CLK_GXL_SDIO
[all …]
A Daml-axg-blocks.h19 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 0}, // CLK_AXG_DDR
22 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 5}, // CLK_AXG_ISA
23 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 6}, // CLK_AXG_PL301
26 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 9}, // CLK_AXG_I2C
27 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 12}, // CLK_AXG_RNG0
28 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 13}, // CLK_AXG_UART0
37 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 27}, // CLK_AXG_DMA
38 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 30}, // CLK_AXG_SPI
44 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 20}, // CLK_AXG_G2D
61 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 30}, // CLK_AXG_GIC
[all …]
A Daml-g12b-blocks.h30 {.reg = G12B_HHI_SYS_CPU_CLK_CNTL1, .bit = 24}, // G12B_CLK_SYS_PLL_DIV16
31 {.reg = G12B_HHI_SYS_CPU_CLK_CNTL1, .bit = 1}, // G12B_CLK_SYS_CPU_CLK_DIV16
32 {.reg = G12B_HHI_XTAL_DIVN_CNTL, .bit = 11}, // G12B_CLK_CAM_INCK_24M
A Daml-g12a-blocks.h29 {.reg = G12A_HHI_SYS_CPU_CLK_CNTL1, .bit = 24}, // CLK_SYS_PLL_DIV16
30 {.reg = G12A_HHI_SYS_CPU_CLK_CNTL1, .bit = 1}, // CLK_SYS_CPU_CLK_DIV16
A Daml-clk-blocks.h11 uint32_t bit; // Offset into this register. member
/system/dev/clk/hisi3660/
A Dhisi3660-clk.c26 { .reg = 0x0, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI },
27 { .reg = 0x0, .bit = 21, .flags = HISI_CLK_FLAG_BANK_PERI },
28 { .reg = 0x0, .bit = 30, .flags = HISI_CLK_FLAG_BANK_PERI },
29 { .reg = 0x0, .bit = 31, .flags = HISI_CLK_FLAG_BANK_PERI },
30 { .reg = 0x10, .bit = 0, .flags = HISI_CLK_FLAG_BANK_PERI },
31 { .reg = 0x10, .bit = 1, .flags = HISI_CLK_FLAG_BANK_PERI },
32 { .reg = 0x10, .bit = 2, .flags = HISI_CLK_FLAG_BANK_PERI },
33 { .reg = 0x10, .bit = 3, .flags = HISI_CLK_FLAG_BANK_PERI },
34 { .reg = 0x10, .bit = 4, .flags = HISI_CLK_FLAG_BANK_PERI },
35 { .reg = 0x10, .bit = 5, .flags = HISI_CLK_FLAG_BANK_PERI },
[all …]
/system/dev/display/intel-i915/
A Dregisters-dpll.h32 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_hdmi_mode()
37 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_ssc_enable()
42 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 2, bit); in dpll_link_rate()
52 int bit = dpll * 6; in dpll_override() local
53 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_override()
63 int bit = 15 + ddi; in ddi_clock_off() local
64 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_clock_off()
69 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 1, bit); in ddi_clock_select()
73 int bit = ddi * 3; in ddi_select_override() local
74 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_select_override()
[all …]
A Dregisters-ddi.h30 uint32_t bit; in ddi_bit() local
33 bit = 24; in ddi_bit()
38 bit = 20 + ddi; in ddi_bit()
41 bit = 25; in ddi_bit()
44 bit = -1; in ddi_bit()
46 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_bit()
57 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_enable()
62 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_long_pulse()
67 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_short_pulse()
142 int bit = 8 + 3 * ddi; in tx_balance_leg_select() local
[all …]
A Ddpcd.h89 int bit = 4 * (lane % 2); in lane_cr_done() local
90 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_cr_done()
94 int bit = 4 * (lane % 2) + 1; in lane_channel_eq_done() local
95 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_channel_eq_done()
99 int bit = 4 * (lane % 2) + 2; in lane_symbol_locked() local
100 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_symbol_locked()
108 int bit = 4 * (lane % 2); in voltage_swing() local
109 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit + 1, bit); in voltage_swing()
113 int bit = 4 * (lane % 2) + 2; in pre_emphasis() local
114 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit + 1, bit); in pre_emphasis()
A Dregisters.h131 int bit = 2 + ((ddi == DDI_A || ddi == DDI_E) ? 0 : ddi * 2) + 1; in ddi_io_power_request() local
132 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_io_power_request()
136 int bit = 2 + ((ddi == DDI_A || ddi == DDI_E) ? 0 : ddi * 2); in ddi_io_power_state() local
137 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_io_power_state()
/system/dev/gpio/pl061/
A Dpl061.c29 uint8_t bit = 1 << (index % GPIOS_PER_PAGE); in pl061_gpio_config_in() local
33 dir &= ~bit; in pl061_gpio_config_in()
75 uint8_t bit = 1 << (index % GPIOS_PER_PAGE); in pl061_gpio_config_out() local
79 writeb((initial_value ? bit : 0), regs + GPIODATA(bit)); in pl061_gpio_config_out()
83 dir |= bit; in pl061_gpio_config_out()
98 uint8_t bit = 1 << (index % GPIOS_PER_PAGE); in pl061_gpio_read() local
100 *out_value = !!(readb(regs + GPIODATA(bit)) & bit); in pl061_gpio_read()
108 uint8_t bit = 1 << (index % GPIOS_PER_PAGE); in pl061_gpio_write() local
110 writeb((value ? bit : 0), regs + GPIODATA(bit)); in pl061_gpio_write()
/system/dev/clk/mtk-clk/
A Dmtk-clk.cpp26 const uint8_t bit; member
34 [board_mt8167::kClkThermal] = {.regs = kClkGatingCtrl1, .bit = 1},
35 [board_mt8167::kClkI2c0] = {.regs = kClkGatingCtrl1, .bit = 3},
36 [board_mt8167::kClkI2c1] = {.regs = kClkGatingCtrl1, .bit = 4},
37 [board_mt8167::kClkI2c2] = {.regs = kClkGatingCtrl1, .bit = 16},
40 [board_mt8167::kClkAuxAdc] = {.regs = kClkGatingCtrl1, .bit = 30},
41 [board_mt8167::kClkSlowMfg] = {.regs = kClkGatingCtrl8, .bit = 7},
42 [board_mt8167::kClkAxiMfg] = {.regs = kClkGatingCtrl8, .bit = 6},
43 [board_mt8167::kClkMfgMm] = {.regs = kClkGatingCtrl0, .bit = 2},
153 mmio_.Write32(1 << gate.bit, gate.regs.clr); in ClkEnable()
[all …]
/system/dev/clk/hisi-lib/
A Dhisi-clk.c61 const uint32_t bit, const bool enable) { in hisi_sep_clk_toggle_locked() argument
62 const uint32_t val = 1 << bit; in hisi_sep_clk_toggle_locked()
76 const uint32_t bit, const bool enable) { in hisi_gate_clk_toggle_locked() argument
80 val |= 1 << bit; in hisi_gate_clk_toggle_locked()
82 val &= ~(1 << bit); in hisi_gate_clk_toggle_locked()
103 hisi_gate_clk_toggle_locked(base + gate->reg, gate->bit, enable); in hisi_clk_toggle()
107 hisi_sep_clk_toggle_locked(base + gate->reg, gate->bit, enable); in hisi_clk_toggle()
/system/banjo/ddk-protocol-sdhci/
A Dsdhci.banjo11 /// bit response are normally filled by 7 CRC bits and 1 reserved bit.
22 /// The bottom 8 bits of the 136 bit response are normally filled by 7 CRC bits
23 /// and 1 reserved bit. Some controllers strip off the CRC.
/system/dev/bus/virtio/backends/
A Dbackend.h32 virtual bool ReadFeature(uint32_t bit) = 0;
34 virtual void SetFeature(uint32_t bit) = 0;
A Dpci_modern.cpp297 uint32_t bit = feature % 32; in ReadFeature() local
302 bool is_set = (val & (1u << bit)) != 0; in ReadFeature()
310 uint32_t bit = feature % 32; in SetFeature() local
315 MmioWrite(&common_cfg_->driver_feature, val | (1u << bit)); in SetFeature()
/system/uapp/aslr-analysis/
A Dmain.cpp119 for (unsigned int bit = 0; bit < sizeof(uintptr_t) * 8; ++bit) { in AnalyzeField() local
123 if (val & (1ULL << bit)) { in AnalyzeField()
/system/utest/fbl/include/fbl/tests/
A Dlfsr.h42 bool bit = core_ & 1u; in GetNext() local
44 if (bit) { in GetNext()
/system/dev/clk/hisi-lib/include/dev/clk/hisi-lib/
A Dhisi.h16 uint32_t bit; // Offset into this register. member
/system/banjo/zircon-device-nand/
A Dnand.banjo15 /// Number of ECC bits (correctable bit flips), per correction chunk.
/system/dev/input/pc-ps2/
A Di8042.c51 int bit = mod - HID_USAGE_KEY_LEFT_CTRL; in i8042_modifier_key() local
52 if (bit < 0 || bit > 7) return MOD_ROLLOVER; in i8042_modifier_key()
54 if (dev->report.kbd.modifier & 1 << bit) { in i8042_modifier_key()
57 dev->report.kbd.modifier |= 1 << bit; in i8042_modifier_key()
60 dev->report.kbd.modifier &= ~(1 << bit); in i8042_modifier_key()
/system/dev/display/astro-display/
A Ddw-mipi-dsi.h39 zx_status_t WaitforFifo(uint32_t reg, uint32_t bit, uint32_t val);
/system/fidl/fuchsia-hardware-nand/
A Dnand.fidl22 uint32 ecc_bits; // Number of ECC bits (correctable bit flips),
/system/ulib/test-utils/
A DREADME.md9 It's possible to be a bit more clever but for the particular
/system/dev/usb/usb-hub/
A Dusb-hub.c388 int bit = 1; in usb_hub_thread() local
390 if (*bitmap & (1 << bit)) { in usb_hub_thread()
398 if (++bit == 8) { in usb_hub_thread()
400 bit = 0; in usb_hub_thread()

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