1 // Copyright 2018 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #pragma once
6 
7 #include <assert.h>
8 #include <hwreg/bitfields.h>
9 #include <hwreg/mmio.h>
10 
11 namespace registers {
12 class VdIfGenReg : public hwreg::RegisterBase<VdIfGenReg, uint32_t> {
13 public:
14     static constexpr uint32_t kBaseAddr = 0x1a50;
15 
16     DEF_BIT(31, enable_free_clock);
17     DEF_BIT(30, sw_reset);
18     DEF_BIT(29, reset_on_go_field);
19     DEF_BIT(28, urgent_chroma);
20     DEF_BIT(27, urgent_luma);
21     DEF_BIT(26, chroma_end_at_last_line);
22     DEF_BIT(25, luma_end_at_last_line);
23     DEF_FIELD(24, 19, hold_lines);
24     DEF_BIT(18, last_line);
25     DEF_BIT(17, busy);
26     DEF_BIT(16, demux_mode);
27     DEF_FIELD(15, 14, bytes_per_pixel);
28     DEF_FIELD(13, 12, ddr_burst_size_cr);
29     DEF_FIELD(11, 10, ddr_burst_size_cb);
30     DEF_FIELD(9, 8, ddr_burst_size_y);
31     DEF_BIT(7, manual_start_frame);
32     DEF_BIT(6, chro_rpt_lastl_ctrl);
33     // This seems to do a 128-bit endianness conversion, which isn't very useful. The canvas should
34     // be used to do the conversion instead.
35     DEF_BIT(4, little_endian);
36     DEF_BIT(3, chroma_hz_avg);
37     DEF_BIT(2, luma_hz_avg);
38     DEF_BIT(1, separate_en);
39     DEF_BIT(0, enable);
40 };
41 
42 class VdIfCanvas0 : public hwreg::RegisterBase<VdIfCanvas0, uint32_t> {
43 public:
44     static constexpr uint32_t kBaseAddr = 0x1a51;
45 };
46 
47 class VdIfLumaX0 : public hwreg::RegisterBase<VdIfLumaX0, uint32_t> {
48 public:
49     static constexpr uint32_t kBaseAddr = 0x1a53;
50     DEF_FIELD(30, 16, end);
51     DEF_FIELD(14, 0, start);
52 };
53 
54 class VdIfLumaY0 : public hwreg::RegisterBase<VdIfLumaY0, uint32_t> {
55 public:
56     static constexpr uint32_t kBaseAddr = 0x1a54;
57     DEF_FIELD(28, 16, end);
58     DEF_FIELD(12, 0, start);
59 };
60 
61 class VdIfChromaX0 : public hwreg::RegisterBase<VdIfChromaX0, uint32_t> {
62 public:
63     static constexpr uint32_t kBaseAddr = 0x1a55;
64     DEF_FIELD(30, 16, end);
65     DEF_FIELD(14, 0, start);
66 };
67 
68 class VdIfChromaY0 : public hwreg::RegisterBase<VdIfChromaY0, uint32_t> {
69 public:
70     static constexpr uint32_t kBaseAddr = 0x1a56;
71     DEF_FIELD(28, 16, end);
72     DEF_FIELD(12, 0, start);
73 };
74 
75 class VdIfGenReg2 : public hwreg::RegisterBase<VdIfGenReg2, uint32_t> {
76 public:
77     static constexpr uint32_t kBaseAddr = 0x1a6d;
78 
79     DEF_FIELD(1, 0, color_map);
80 };
81 
82 class VdFmtCtrl : public hwreg::RegisterBase<VdFmtCtrl, uint32_t> {
83 public:
84     static constexpr uint32_t kBaseAddr = 0x1a68;
85 
86     DEF_BIT(31, gate_clk_en);
87     DEF_BIT(30, soft_rst);
88     DEF_BIT(28, horizontal_repeat);
89     DEF_FIELD(27, 24, horizontal_initial_phase);
90     DEF_BIT(23, horizontal_repeat_pixel0);
91     DEF_FIELD(22, 21, horizontal_yc_ratio);
92     DEF_BIT(20, horizontal_enable);
93     DEF_BIT(19, virtual_phase0_only);
94     DEF_BIT(18, disable_vertical_chroma_repeat);
95     DEF_BIT(17, disable_vertical_repeat_line);
96     DEF_BIT(16, vertical_repeat_line0);
97     DEF_FIELD(15, 12, vertical_skip_line_num);
98     DEF_FIELD(11, 8, vertical_initial_phase);
99     DEF_FIELD(7, 1, vertical_phase_step);
100     DEF_BIT(0, vertical_enable);
101 };
102 
103 class VdFmtW : public hwreg::RegisterBase<VdFmtW, uint32_t> {
104 public:
105     static constexpr uint32_t kBaseAddr = 0x1a69;
106     DEF_FIELD(27, 16, horizontal_width);
107     DEF_FIELD(11, 0, vertical_width);
108 };
109 
110 class VdIfRptLoop : public hwreg::RegisterBase<VdIfRptLoop, uint32_t> {
111 public:
112     static constexpr uint32_t kBaseAddr = 0x1a5b;
113 };
114 
115 class VdIfLuma0RptPat : public hwreg::RegisterBase<VdIfLuma0RptPat, uint32_t> {
116 public:
117     static constexpr uint32_t kBaseAddr = 0x1a5c;
118 };
119 
120 class VdIfChroma0RptPat : public hwreg::RegisterBase<VdIfChroma0RptPat, uint32_t> {
121 public:
122     static constexpr uint32_t kBaseAddr = 0x1a5d;
123 };
124 
125 class VdIfLumaPsel : public hwreg::RegisterBase<VdIfLumaPsel, uint32_t> {
126 public:
127     static constexpr uint32_t kBaseAddr = 0x1a60;
128 };
129 
130 class VdIfChromaPsel : public hwreg::RegisterBase<VdIfChromaPsel, uint32_t> {
131 public:
132     static constexpr uint32_t kBaseAddr = 0x1a61;
133 };
134 
135 class Vd {
136 public:
137     // 0-based index
Vd(uint32_t index)138     Vd(uint32_t index) : index_(index) { assert(index < 2); }
139 
IfGenReg()140     auto IfGenReg() { return GetReg<VdIfGenReg>(); }
IfCanvas0()141     auto IfCanvas0() { return GetReg<VdIfCanvas0>(); }
IfLumaX0()142     auto IfLumaX0() { return GetReg<VdIfLumaX0>(); }
IfLumaY0()143     auto IfLumaY0() { return GetReg<VdIfLumaY0>(); }
IfChromaX0()144     auto IfChromaX0() { return GetReg<VdIfChromaX0>(); }
IfChromaY0()145     auto IfChromaY0() { return GetReg<VdIfChromaY0>(); }
IfGenReg2()146     auto IfGenReg2() { return GetReg<VdIfGenReg2>(); }
FmtCtrl()147     auto FmtCtrl() { return GetReg<VdFmtCtrl>(); }
FmtW()148     auto FmtW() { return GetReg<VdFmtW>(); }
IfRptLoop()149     auto IfRptLoop() { return GetReg<VdIfRptLoop>(); }
IfLuma0RptPat()150     auto IfLuma0RptPat() { return GetReg<VdIfLuma0RptPat>(); }
IfChroma0RptPat()151     auto IfChroma0RptPat() { return GetReg<VdIfChroma0RptPat>(); }
IfLumaPsel()152     auto IfLumaPsel() { return GetReg<VdIfLumaPsel>(); }
IfChromaPsel()153     auto IfChromaPsel() { return GetReg<VdIfChromaPsel>(); }
154 
155 private:
GetReg()156     template <class RegType> hwreg::RegisterAddr<RegType> GetReg() {
157         return hwreg::RegisterAddr<RegType>((RegType::kBaseAddr + 0x20 * index_) * 4);
158     }
159     uint32_t index_;
160 };
161 
162 class VpuVppMisc : public hwreg::RegisterBase<VpuVppMisc, uint32_t> {
163 public:
Get()164     static auto Get() { return hwreg::RegisterAddr<VpuVppMisc>(0x1d26 * 4); }
165 
166     DEF_BIT(13, osd2_enable_postblend);
167     DEF_BIT(12, osd1_enable_postblend);
168     DEF_BIT(11, vd2_enable_postblend);
169     DEF_BIT(10, vd1_enable_postblend);
170 };
171 
172 class VpuVppOsdScCtrl0 : public hwreg::RegisterBase<VpuVppOsdScCtrl0, uint32_t> {
173 public:
Get()174     static auto Get() { return hwreg::RegisterAddr<VpuVppOsdScCtrl0>(0x1dc8 * 4); }
175 
176     enum {
177         kSelectOsd1 = 0,
178         kSelectOsd2 = 1,
179         kSelectVd1 = 2,
180         kSelectVd2 = 3,
181     };
182 
183     DEF_BIT(3, enable);
184     DEF_FIELD(1, 0, osd_sc_sel);
185 };
186 
187 class VpuVppOsdScoHStartEnd : public hwreg::RegisterBase<VpuVppOsdScoHStartEnd, uint32_t> {
188 public:
Get()189     static auto Get() { return hwreg::RegisterAddr<VpuVppOsdScoHStartEnd>(0x1dca * 4); }
190     DEF_FIELD(27, 16, output_horizontal_start);
191     DEF_FIELD(11, 0, output_horizontal_end);
192 };
193 
194 class VpuVppOsdScoVStartEnd : public hwreg::RegisterBase<VpuVppOsdScoVStartEnd, uint32_t> {
195 public:
Get()196     static auto Get() { return hwreg::RegisterAddr<VpuVppOsdScoVStartEnd>(0x1dcb * 4); }
197     DEF_FIELD(27, 16, output_vertial_start);
198     DEF_FIELD(11, 0, output_vertical_end);
199 };
200 
201 class VpuVppOsdSciWhM1 : public hwreg::RegisterBase<VpuVppOsdSciWhM1, uint32_t> {
202 public:
Get()203     static auto Get() { return hwreg::RegisterAddr<VpuVppOsdSciWhM1>(0x1dc9 * 4); }
204     DEF_FIELD(28, 16, input_width_minus1);
205     DEF_FIELD(12, 0, input_height_minus1);
206 };
207 
208 class VpuVppPostblendHSize : public hwreg::RegisterBase<VpuVppPostblendHSize, uint32_t> {
209 public:
Get()210     static auto Get() { return hwreg::RegisterAddr<VpuVppPostblendHSize>(0x1d21 * 4); }
211     DEF_FIELD(11, 0, horizontal_size);
212 };
213 
214 class VpuViuOsdBlk0CfgW0 : public hwreg::RegisterBase<VpuViuOsdBlk0CfgW0, uint32_t> {
215 public:
216     static constexpr uint32_t kBaseAddr = 0x1a1b;
217 
218     enum {
219         kColorMatrix655 = 0,
220         kColorMatrix844 = 1,
221         kColorMatrix565 = 2,
222 
223         kColorMatrixRGBA8888 = 0,
224         kColorMatrixARGB8888 = 1,
225         kColorMatrixABGR8888 = 2,
226         kColorMatrixBGRA8888 = 3,
227 
228         kColorMatrixRGB888 = 0,
229         kColorMatrixBGR888 = 5,
230     };
231     enum {
232         kBlockMode422 = 3,
233         kBlockMode16Bit = 4,
234         kBlockMode32Bit = 5,
235         kBlockMode24Bit = 7,
236     };
237 
238 
239     DEF_BIT(29, y_rev);
240     DEF_BIT(28, x_rev);
241     DEF_FIELD(23, 16, tbl_addr);
242     DEF_BIT(15, little_endian);
243     DEF_BIT(14, rpt_y);
244     DEF_FIELD(13, 12, interp_ctrl);
245     DEF_FIELD(11, 8, block_mode);
246     DEF_BIT(7, rgb_en);
247     DEF_BIT(6, tx_alpha_en);
248     DEF_FIELD(5, 2, color_matrix);
249     DEF_BIT(1, interlace_en);
250     DEF_BIT(0, interlace_sel_odd);
251 };
252 
253 class VpuViuOsdBlk0CfgW1 : public hwreg::RegisterBase<VpuViuOsdBlk0CfgW1, uint32_t> {
254 public:
255     static constexpr uint32_t kBaseAddr = 0x1a1c;
256 
257     DEF_FIELD(28, 16, virtual_canvas_x_end);
258     DEF_FIELD(12, 0, virtual_canvas_x_start);
259 };
260 
261 class VpuViuOsdBlk0CfgW2 : public hwreg::RegisterBase<VpuViuOsdBlk0CfgW2, uint32_t> {
262 public:
263     static constexpr uint32_t kBaseAddr = 0x1a1d;
264 
265     DEF_FIELD(28, 16, virtual_canvas_y_end);
266     DEF_FIELD(12, 0, virtual_canvas_y_start);
267 };
268 
269 class VpuViuOsdBlk0CfgW3 : public hwreg::RegisterBase<VpuViuOsdBlk0CfgW3, uint32_t> {
270 public:
271     static constexpr uint32_t kBaseAddr = 0x1a1e;
272 
273     DEF_FIELD(28, 16, display_h_end);
274     DEF_FIELD(12, 0, display_h_start);
275 };
276 
277 class VpuViuOsdBlk0CfgW4 : public hwreg::RegisterBase<VpuViuOsdBlk0CfgW4, uint32_t> {
278 public:
279     static constexpr uint32_t kBaseAddresses[2] = {0x1a13, 0x1a64};
280     DEF_FIELD(28, 16, display_v_end);
281     DEF_FIELD(12, 0, display_v_start);
282 };
283 
284 class VpuViuOsdCtrlStat2 : public hwreg::RegisterBase<VpuViuOsdCtrlStat2, uint32_t> {
285 public:
286     static constexpr uint32_t kBaseAddr = 0x1a2d;
287 
288     DEF_BIT(15, osd_dpath_sel);
289     DEF_BIT(14, replaced_alpha_en);
290     DEF_FIELD(13, 6, replaced_alpha);
291     DEF_FIELD(5, 4, hold_fifo_lines);
292     DEF_BIT(3, rgbyuv_full_range);
293     DEF_BIT(2, alpha_9b_mode);
294     DEF_BIT(0, color_expand_mode);
295 };
296 
297 class VpuViuOsdCtrlStat : public hwreg::RegisterBase<VpuViuOsdCtrlStat, uint32_t> {
298 public:
299     static constexpr uint32_t kBaseAddr = 0x1a10;
300 
301     DEF_BIT(30, enable_free_clock);
302     DEF_BIT(28, osd_done);
303     DEF_FIELD(27, 24, osd_blk_mode);
304     DEF_FIELD(23, 22, osd_blk_ptr);
305     DEF_BIT(21, osd_enable);
306     DEF_FIELD(20, 12, global_alpha);
307     DEF_FIELD(8, 5, ctrl_mtch_y);
308     DEF_BIT(4, ctrl_422to444);
309     DEF_BIT(0, osd_blk_enable);
310 };
311 
312 class Osd {
313 public:
314     // 0-based OSD index
Osd(uint32_t index)315     Osd(uint32_t index)
316         : index_(index) { assert(index_ < 2); }
317 
CtrlStat()318     auto CtrlStat() { return GetReg<registers::VpuViuOsdCtrlStat>(); }
CtrlStat2()319     auto CtrlStat2() { return GetReg<registers::VpuViuOsdCtrlStat2>(); }
320 
Blk0CfgW0()321     auto Blk0CfgW0() { return GetReg<registers::VpuViuOsdBlk0CfgW0>(); }
Blk0CfgW1()322     auto Blk0CfgW1() { return GetReg<registers::VpuViuOsdBlk0CfgW1>(); }
Blk0CfgW2()323     auto Blk0CfgW2() { return GetReg<registers::VpuViuOsdBlk0CfgW2>(); }
Blk0CfgW3()324     auto Blk0CfgW3() { return GetReg<registers::VpuViuOsdBlk0CfgW3>(); }
Blk0CfgW4()325     auto Blk0CfgW4() { return GetRegNonstandard<registers::VpuViuOsdBlk0CfgW4>(); }
326 
327 private:
328     template <class RegType>
GetReg()329     hwreg::RegisterAddr<RegType> GetReg() {
330         return hwreg::RegisterAddr<RegType>((RegType::kBaseAddr + 0x20 * index_) * 4);
331     }
332 
333     template <class RegType>
GetRegNonstandard()334     hwreg::RegisterAddr<RegType> GetRegNonstandard() {
335         ZX_DEBUG_ASSERT(index_ < countof(RegType::kBaseAddresses));
336         return hwreg::RegisterAddr<RegType>(RegType::kBaseAddresses[index_] * 4);
337     }
338 
339     const uint32_t index_;
340 };
341 }  // namespace registers
342