Searched refs:reg_val (Results 1 – 3 of 3) sorted by relevance
| /system/dev/board/imx8mevk/ |
| A D | imx8mevk-gpu.c | 71 uint32_t reg_val = 0; in core_clock_init() local
72 reg_val |= (ENABLE << 28); // enable: 1 bit in core_clock_init()
73 reg_val |= (IMX8_GPU_PLL_CLK << 24); // mux: 3 bits. in core_clock_init()
76 writel(reg_val, ccm_regs + kOffset); in core_clock_init()
94 uint32_t reg_val = 0; in shader_clock_init() local
96 reg_val |= (IMX8_GPU_PLL_CLK << 24); // mux: 3 bits. in shader_clock_init()
99 writel(reg_val, ccm_regs + kOffset); in shader_clock_init()
118 uint32_t reg_val = 0; in axi_clock_init() local
123 writel(reg_val, ccm_regs + kOffset); in axi_clock_init()
141 uint32_t reg_val = 0; in ahb_clock_init() local
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| /system/dev/lib/amlogic/ |
| A D | s905d2-hiu.c | 105 uint32_t reg_val = hiu_clk_get_reg(pll_dev->hiu, offs); in s905d2_pll_ena() local
108 reg_val |= HHI_PLL_CNTL0_EN; in s905d2_pll_ena()
109 hiu_clk_set_reg(pll_dev->hiu, offs, reg_val); in s905d2_pll_ena()
113 reg_val &= ~HHI_PLL_CNTL0_RESET; in s905d2_pll_ena()
114 hiu_clk_set_reg(pll_dev->hiu, offs, reg_val); in s905d2_pll_ena()
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| /system/dev/display/vim-display/ |
| A D | hdmitx.cpp | 883 unsigned int reg_val; in dump_regs() local
887 reg_val = READ32_REG(HHI, ladr); in dump_regs()
888 DISP_INFO("[0x%08x] = 0x%X\n", ladr, reg_val); in dump_regs()
893 reg_val = READ32_REG(VPU, ladr); in dump_regs()
894 DISP_INFO("[0x%08x] = 0x%X\n", ladr, reg_val); in dump_regs()
898 reg_val = READ32_REG(VPU, ladr); in dump_regs()
899 DISP_INFO("[0x%08x] = 0x%X\n", ladr, reg_val); in dump_regs()
903 reg_val = READ32_REG(VPU, ladr); in dump_regs()
907 reg_val = hdmitx_readreg(display, reg_adr); in dump_regs()
912 reg_val = 0; in dump_regs()
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