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Searched refs:reg_value_ptr (Results 1 – 10 of 10) sorted by relevance

/system/dev/display/intel-i915/
A Dregisters-dpll.h32 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_hdmi_mode()
37 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_ssc_enable()
42 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 2, bit); in dpll_link_rate()
53 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_override()
64 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_clock_off()
69 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 1, bit); in ddi_clock_select()
74 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_select_override()
147 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in dpll_lock()
A Dregisters-ddi.h46 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_bit()
57 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_enable()
62 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_long_pulse()
67 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in hpd_short_pulse()
143 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 2, bit); in tx_balance_leg_select()
A Ddpcd.h90 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_cr_done()
95 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_channel_eq_done()
100 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); in lane_symbol_locked()
109 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit + 1, bit); in voltage_swing()
114 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit + 1, bit); in pre_emphasis()
A Ddp-display.cpp684 || !DpcdWrite(dpcd::DPCD_COUNT_SET, lc_setting.reg_value_ptr(), 1)) { in LinkTrainingSetup()
900 if (!DpcdRead(dpcd::DPCD_SINK_COUNT, sink_count.reg_value_ptr(), 1)) { in Query()
1024 while (!DpcdWrite(dpcd::DPCD_SET_POWER, set_pwr.reg_value_ptr(), 1) && ++count < 5) { in InitDdi()
1034 if (!DpcdRead(dpcd::DPCD_LANE_ALIGN_STATUS_UPDATED, status.reg_value_ptr(), 1)) { in InitDdi()
1215 if (!DpcdWrite(dpcd::DPCD_EDP_BACKLIGHT_MODE_SET, mode.reg_value_ptr(), 1)) { in InitBacklightHw()
1231 if (!DpcdWrite(dpcd::DPCD_EDP_DISPLAY_CTRL, ctrl.reg_value_ptr(), 1)) { in SetBacklightOn()
1254 if (!DpcdRead(dpcd::DPCD_EDP_DISPLAY_CTRL, ctrl.reg_value_ptr(), 1)) { in IsBacklightOn()
1334 if (!DpcdRead(dpcd::DPCD_SINK_COUNT, sink_count.reg_value_ptr(), 1)) { in HandleHotplug()
1351 if (!DpcdRead(dpcd::DPCD_LANE_ALIGN_STATUS_UPDATED, status.reg_value_ptr(), 1)) { in HandleHotplug()
A Dregisters.h132 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_io_power_request()
137 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); in ddi_io_power_state()
A Dgtt.cpp70 gmch_gfx_ctrl.reg_value_ptr()); in Init()
A Dregisters-pipe.h299 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 15, bit); in coefficient()
A Dintel-i915.cpp1837 pci_config_read32(&pci_, bdsm_reg.kAddr, bdsm_reg.reg_value_ptr()); in DdkSuspend()
/system/ulib/hwreg/include/hwreg/
A Dbitfields.h111 ValueType* reg_value_ptr() { return &reg_value_; } in reg_value_ptr() function
112 const ValueType* reg_value_ptr() const { return &reg_value_; } in reg_value_ptr() function
256 return hwreg::BitfieldRef<const ValueType>(reg_value_ptr(), (BIT_HIGH), (BIT_LOW)).get(); \
259 hwreg::BitfieldRef<ValueType>(reg_value_ptr(), (BIT_HIGH), (BIT_LOW)).set(val); \
/system/dev/usb/dwc3/
A Ddwc3-regs.h240 *reg_value_ptr() |= (1 << ep); in EnableEp()
245 *reg_value_ptr() &= ~(1 << ep); in DisableEp()

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