1// Copyright 2018 The Fuchsia Authors 2// 3// Use of this source code is governed by a MIT-style 4// license that can be found in the LICENSE file or at 5// https://opensource.org/licenses/MIT 6 7#include <asm.h> 8#include <arch/asm_macros.h> 9#include <zircon/boot/image.h> 10 11#define SCTLR_I (1 << 12) // Instruction cache enable 12#define SCTLR_C (1 << 2) // Cache enable 13#define SCTLR_M (1 << 0) // MMU enable 14 15// scratch register, not saved across function calls 16tmp .req x16 17 18#define STACK_SIZE 4096 19 20.section .text.boot0,"ax" 21FUNCTION(_start) 22 // magic instruction that gives us UEFI "MZ" signature 23 add x13, x18, #0x16 24 b header_end 25 26 .quad 0 // image offset from start of ram (unused) 27 .quad 0 // image size (unused) 28 .quad 0 29 .quad 0 30 .quad 0 31 .quad 0 32 33 // arm64 magic number 34 .byte 'A' 35 .byte 'R' 36 .byte 'M' 37 .byte 0x64 38 .align 3 39 40header_end: 41 // x0 typically points to device tree at entry 42 43 // what EL are we running at? 44 mrs tmp, CurrentEL 45 cmp tmp, #(1 << 2) 46 beq cache_disable_el1 47 48 // Disable caches and MMU (EL2 version) 49 mrs tmp, sctlr_el2 50 bic tmp, tmp, #SCTLR_I 51 bic tmp, tmp, #SCTLR_C 52 bic tmp, tmp, #SCTLR_M 53 msr sctlr_el2, tmp 54 b cache_disable_done 55 56cache_disable_el1: 57 // Disable caches and MMU (EL1 version) 58 mrs tmp, sctlr_el1 59 bic tmp, tmp, #SCTLR_I 60 bic tmp, tmp, #SCTLR_C 61 bic tmp, tmp, #SCTLR_M 62 msr sctlr_el1, tmp 63 64cache_disable_done: 65 // setup stack 66 adr tmp, stack_end 67 mov sp, tmp 68 69 // x0: pointer to device tree 70 bl boot_shim 71 72 // x0: bootdata_t* to pass to kernel 73 // x1: kernel entry point 74 br x1 75END_FUNCTION(_start) 76 77.bss 78.balign 16 79LOCAL_DATA(stack) 80 .skip STACK_SIZE 81LOCAL_DATA(stack_end) 82END_DATA(stack) 83