1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #include "aml-clk-blocks.h" 8 #include <soc/aml-meson/axg-clk.h> 9 10 #define AXG_HHI_PCIE_PLL_CNTL6 (0x3C << 2) 11 #define AXG_HHI_GCLK_MPEG0 (0x50 << 2) 12 #define AXG_HHI_GCLK_MPEG1 (0x51 << 2) 13 #define AXG_HHI_GCLK_MPEG2 (0x52 << 2) 14 #define AXG_HHI_GCLK_AO (0x55 << 2) 15 #define AXG_HHI_MPEG_CLK_CNTL (0x5D << 2) 16 17 static meson_clk_gate_t axg_clk_gates[] = { 18 // MPEG0 Clock Gates 19 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 0}, // CLK_AXG_DDR 20 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 2}, // CLK_AXG_AUDIO_LOCKER 21 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 3}, // CLK_AXG_MIPI_DSI_HOST 22 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 5}, // CLK_AXG_ISA 23 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 6}, // CLK_AXG_PL301 24 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 7}, // CLK_AXG_PERIPHS 25 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 8}, // CLK_AXG_SPICC_0 26 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 9}, // CLK_AXG_I2C 27 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 12}, // CLK_AXG_RNG0 28 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 13}, // CLK_AXG_UART0 29 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 14}, // CLK_AXG_MIPI_DSI_PHY 30 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 15}, // CLK_AXG_SPICC_1 31 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 16}, // CLK_AXG_PCIE_A 32 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 17}, // CLK_AXG_PCIE_B 33 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 19}, // CLK_AXG_HIU_REG 34 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 23}, // CLK_AXG_ASSIST_MISC 35 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 25}, // CLK_AXG_EMMC_B 36 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 26}, // CLK_AXG_EMMC_C 37 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 27}, // CLK_AXG_DMA 38 {.reg = AXG_HHI_GCLK_MPEG0, .bit = 30}, // CLK_AXG_SPI 39 40 // MPEG1 Clock Gates 41 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 0}, // CLK_AXG_AUDIO 42 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 3}, // CLK_AXG_ETH_CORE 43 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 16}, // CLK_AXG_UART1 44 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 20}, // CLK_AXG_G2D 45 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 21}, // CLK_AXG_USB0 46 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 22}, // CLK_AXG_USB1 47 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 23}, // CLK_AXG_RESET 48 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 26}, // CLK_AXG_USB_GENERAL 49 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 29}, // CLK_AXG_AHB_ARB0 50 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 30}, // CLK_AXG_EFUSE 51 {.reg = AXG_HHI_GCLK_MPEG1, .bit = 31}, // CLK_AXG_BOOT_ROM 52 53 // MPEG2 Clock Gates 54 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 1}, // CLK_AXG_AHB_DATA_BUS 55 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 2}, // CLK_AXG_AHB_CTRL_BUS 56 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 8}, // CLK_AXG_USB1_TO_DDR 57 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 9}, // CLK_AXG_USB0_TO_DDR 58 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 11}, // CLK_AXG_MMC_PCLK 59 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 25}, // CLK_AXG_VPU_INTR 60 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 26}, // CLK_AXG_SEC_AHB_AHB3_BRIDGE 61 {.reg = AXG_HHI_GCLK_MPEG2, .bit = 30}, // CLK_AXG_GIC 62 63 // AO Domain Clock Gates 64 {.reg = AXG_HHI_GCLK_AO, .bit = 0}, // CLK_AXG_AO_MEDIA_CPU 65 {.reg = AXG_HHI_GCLK_AO, .bit = 1}, // CLK_AXG_AO_AHB_SRAM 66 {.reg = AXG_HHI_GCLK_AO, .bit = 2}, // CLK_AXG_AO_AHB_BUS 67 {.reg = AXG_HHI_GCLK_AO, .bit = 3}, // CLK_AXG_AO_IFACE 68 {.reg = AXG_HHI_GCLK_AO, .bit = 4}, // CLK_AXG_AO_I2C 69 70 // Etc... 71 {.reg = AXG_HHI_MPEG_CLK_CNTL, .bit = 7}, // CLK_AXG_CLK81 72 {.reg = AXG_HHI_PCIE_PLL_CNTL6, .bit = 4}, // CLK_CML0_EN 73 }; 74 75 static_assert(CLK_AXG_COUNT == countof(axg_clk_gates), 76 "axg_clk_gates[] and axg_clk_gate_idx count mismatch"); 77 78