1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #pragma once 6 7 #include "aml-clk-blocks.h" 8 #include <soc/aml-meson/gxl-clk.h> 9 10 #define GXL_HHI_GCLK_MPEG0 (0x50 << 2) 11 #define GXL_HHI_GCLK_MPEG1 (0x51 << 2) 12 #define GXL_HHI_GCLK_MPEG2 (0x52 << 2) 13 #define GXL_HHI_GCLK_OTHER (0x54 << 2) 14 15 static meson_clk_gate_t gxl_clk_gates[] = { 16 // MPEG0 Domain Clocks 17 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 0}, // CLK_GXL_DDR 18 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 1}, // CLK_GXL_DOS 19 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 5}, // CLK_GXL_ISA 20 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 6}, // CLK_GXL_PL301 21 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 7}, // CLK_GXL_PERIPHS 22 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 8}, // CLK_GXL_SPICC 23 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 9}, // CLK_GXL_I2C 24 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 10}, // CLK_GXL_SANA 25 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 11}, // CLK_GXL_SMART_CARD 26 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 12}, // CLK_GXL_RNG0 27 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 13}, // CLK_GXL_UART0 28 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 14}, // CLK_GXL_SDHC 29 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 15}, // CLK_GXL_STREAM 30 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 16}, // CLK_GXL_ASYNC_FIFO 31 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 17}, // CLK_GXL_SDIO 32 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 18}, // CLK_GXL_ABUF 33 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 19}, // CLK_GXL_HIU_IFACE 34 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 22}, // CLK_GXL_BT656 35 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 23}, // CLK_GXL_ASSIST_MISC 36 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 24}, // CLK_GXL_EMMC_A 37 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 25}, // CLK_GXL_EMMC_B 38 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 26}, // CLK_GXL_EMMC_C 39 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 27}, // CLK_GXL_DMA 40 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 28}, // CLK_GXL_ACODEC 41 {.reg = GXL_HHI_GCLK_MPEG0, .bit = 30}, // CLK_GXL_SPI 42 43 // MPEG1 Domain Clocks 44 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 0}, // CLK_GXL_PCLK_TVFE 45 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 2}, // CLK_GXL_I2S_SPDIF 46 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 3}, // CLK_GXL_ETH 47 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 4}, // CLK_GXL_DEMUX 48 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 6}, // CLK_GXL_AIU_GLUE 49 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 7}, // CLK_GXL_IEC958 50 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 8}, // CLK_GXL_I2S_OUT 51 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 9}, // CLK_GXL_AMCLK 52 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 10}, // CLK_GXL_AIFIFO2 53 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 11}, // CLK_GXL_MIXER 54 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 12}, // CLK_GXL_MIXER_IFACE 55 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 13}, // CLK_GXL_ADC 56 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 14}, // CLK_GXL_BLKMV 57 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 15}, // CLK_GXL_AIU_TOP 58 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 16}, // CLK_GXL_UART1 59 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 20}, // CLK_GXL_G2D 60 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 21}, // CLK_GXL_USB0 61 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 22}, // CLK_GXL_USB1 62 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 23}, // CLK_GXL_RESET 63 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 24}, // CLK_GXL_NAND 64 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 25}, // CLK_GXL_DOS_PARSER 65 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 26}, // CLK_GXL_USB_GENERAL 66 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 28}, // CLK_GXL_VDIN1 67 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 29}, // CLK_GXL_AHB_ARB0 68 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 30}, // CLK_GXL_EFUSE 69 {.reg = GXL_HHI_GCLK_MPEG1, .bit = 31}, // CLK_GXL_BOOT_ROM 70 71 // MPEG2 Domain Clocks 72 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 1}, // CLK_GXL_AHB_DATA_BUS 73 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 2}, // CLK_GXL_AHB_CTRL_BUS 74 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 3}, // CLK_GXL_HDCP22_PCLK 75 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 4}, // CLK_GXL_HDMITX_PCLK 76 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 5}, // CLK_GXL_PDM_PCLK 77 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 6}, // CLK_GXL_BT656_PCLK 78 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 8}, // CLK_GXL_USB1_TO_DDR 79 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 9}, // CLK_GXL_USB0_TO_DDR 80 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 10}, // CLK_GXL_AIU_PCLK 81 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 11}, // CLK_GXL_MMC_PCLK 82 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 12}, // CLK_GXL_DVIN 83 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 15}, // CLK_GXL_UART2 84 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 22}, // CLK_GXL_SARADC 85 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 25}, // CLK_GXL_VPU_INTR 86 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 26}, // CLK_GXL_SEC_AHB_AHB3_BRIDGE 87 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 27}, // CLK_GXL_APB3_AO 88 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 28}, // CLK_GXL_MCLK_TVFE 89 {.reg = GXL_HHI_GCLK_MPEG2, .bit = 30}, // CLK_GXL_CLK81_GIC 90 91 // Other Domain Clocks 92 {.reg = GXL_HHI_GCLK_OTHER, .bit = 1}, // CLK_GXL_VCLK2_VENCI0 93 {.reg = GXL_HHI_GCLK_OTHER, .bit = 2}, // CLK_GXL_VCLK2_VENCI1 94 {.reg = GXL_HHI_GCLK_OTHER, .bit = 3}, // CLK_GXL_VCLK2_VENCP0 95 {.reg = GXL_HHI_GCLK_OTHER, .bit = 4}, // CLK_GXL_VCLK2_VENCP1 96 {.reg = GXL_HHI_GCLK_OTHER, .bit = 5}, // CLK_GXL_VCLK2_VENCT0 97 {.reg = GXL_HHI_GCLK_OTHER, .bit = 6}, // CLK_GXL_VCLK2_VENCT1 98 {.reg = GXL_HHI_GCLK_OTHER, .bit = 7}, // CLK_GXL_VCLK2_OTHER 99 {.reg = GXL_HHI_GCLK_OTHER, .bit = 8}, // CLK_GXL_VCLK2_ENCI 100 {.reg = GXL_HHI_GCLK_OTHER, .bit = 9}, // CLK_GXL_VCLK2_ENCP 101 {.reg = GXL_HHI_GCLK_OTHER, .bit = 10}, // CLK_GXL_DAC_CLK 102 {.reg = GXL_HHI_GCLK_OTHER, .bit = 14}, // CLK_GXL_AOCLK_GATE 103 {.reg = GXL_HHI_GCLK_OTHER, .bit = 16}, // CLK_GXL_IEC958_GATE 104 {.reg = GXL_HHI_GCLK_OTHER, .bit = 20}, // CLK_GXL_ENC480P 105 {.reg = GXL_HHI_GCLK_OTHER, .bit = 21}, // CLK_GXL_RNG1 106 {.reg = GXL_HHI_GCLK_OTHER, .bit = 22}, // CLK_GXL_VCLK2_ENCT 107 {.reg = GXL_HHI_GCLK_OTHER, .bit = 23}, // CLK_GXL_VCLK2_ENCL 108 {.reg = GXL_HHI_GCLK_OTHER, .bit = 24}, // CLK_GXL_VCLK2_VENCLMMC 109 {.reg = GXL_HHI_GCLK_OTHER, .bit = 25}, // CLK_GXL_VCLK2_VENCL 110 {.reg = GXL_HHI_GCLK_OTHER, .bit = 26}, // CLK_GXL_VCLK2_OTHER1 111 {.reg = GXL_HHI_GCLK_OTHER, .bit = 31}, // CLK_GXL_EDP 112 }; 113 114 static_assert(CLK_GXL_COUNT == countof(gxl_clk_gates), 115 "gxl_clk_gates[] and gxl_clk_gate_idx count mismatch"); 116