1 // Copyright 2017 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #include <ddk/binding.h>
6 #include <ddk/debug.h>
7 #include <ddk/platform-defs.h>
8 #include <ddk/protocol/platform/device.h>
9 #include <ddk/protocol/platform-device-lib.h>
10 #include <stdlib.h>
11 #include <stdio.h>
12 #include <string.h>
13 #include <unistd.h>
14 #include <hw/reg.h>
15 #include <ddk/protocol/i2c.h>
16 #include <ddk/protocol/gpio.h>
17
18 #include "dsi.h"
19 #include "adv7533.h"
20
dsi_get_display_timing(dsi_t * dsi)21 static zx_status_t dsi_get_display_timing(dsi_t* dsi) {
22 zx_status_t status;
23 uint8_t* edid_buf = adv7533_get_edid_buffer();
24 uint8_t num_dtd = 0;
25
26 if (edid_buf == 0) {
27 zxlogf(ERROR, "%s: No EDID available\n", __FUNCTION__);
28 return ZX_ERR_NOT_FOUND;
29 }
30
31 dsi->std_raw_dtd = calloc(1, sizeof(detailed_timing_t));
32 dsi->std_disp_timing = calloc(1, sizeof(disp_timing_t));
33 if (dsi->std_raw_dtd == 0 || dsi->std_disp_timing == 0) {
34 return ZX_ERR_NO_MEMORY;
35 }
36
37 edid_parse_std_display_timing(edid_buf, dsi->std_raw_dtd, dsi->std_disp_timing);
38
39 if ( (status = edid_get_num_dtd(edid_buf, &num_dtd)) != ZX_OK) {
40 zxlogf(ERROR, "Something went wrong with reading number of DTD\n");
41 return status;
42 }
43
44 if (num_dtd == 0) {
45 zxlogf(ERROR, "No DTD Founds!!\n");
46 return ZX_ERR_INTERNAL;
47 }
48
49 zxlogf(INFO, "Number of DTD found was %d\n", num_dtd);
50 dsi->raw_dtd = calloc(num_dtd, sizeof(detailed_timing_t));
51 dsi->disp_timing = calloc(num_dtd, sizeof(disp_timing_t));
52 if (dsi->raw_dtd == 0 || dsi->disp_timing == 0) {
53 return ZX_ERR_NO_MEMORY;
54 }
55
56 edid_parse_display_timing(edid_buf, dsi->raw_dtd, dsi->disp_timing, num_dtd);
57
58 return ZX_OK;
59 }
60
61 /* Unknown DPHY. Use hardcoded values from Android source code for now */
dsi_dphy_write(dsi_t * dsi,uint32_t reg,uint32_t val)62 static void dsi_dphy_write(dsi_t* dsi, uint32_t reg, uint32_t val)
63 {
64
65 // Select phy register
66 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL1, (reg | DW_DSI_PHY_TST_CTRL1_TESTEN));
67 // pulse
68 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL0, DW_DSI_PHY_TST_CTRL0_TSTCLK);
69 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL0, DW_DSI_PHY_TST_CTRL0_TSTCLR);
70
71 // write value (for the register selected above)
72 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL1, val);
73
74 // pulse
75 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL0, DW_DSI_PHY_TST_CTRL0_TSTCLK);
76 DW_DSI_WRITE32(DW_DSI_PHY_TST_CTRL0, DW_DSI_PHY_TST_CTRL0_TSTCLR);
77 }
78
dsi_configure_dphy_pll(dsi_t * dsi)79 static void dsi_configure_dphy_pll(dsi_t* dsi) {
80 uint32_t i;
81 uint32_t tmp = 0;
82
83 dsi_dphy_write(dsi, 0x14, (0x1 << 4) + (0x0 << 3) + (0x0 << 2) + 0x0);
84 dsi_dphy_write(dsi, 0x15, 0x2d);
85 dsi_dphy_write(dsi, 0x16, (0x1 << 5) + (0x0 << 4) +0x1);
86 dsi_dphy_write(dsi, 0x17, 0x2);
87 dsi_dphy_write(dsi, 0x1D, 0x55);
88 dsi_dphy_write(dsi, 0x1E, (0x3 << 5) + (0x1 << 4) + (0x1 << 3) + (0x0 << 2) + (0x0 << 1) + 0x1);
89 dsi_dphy_write(dsi, 0x1F, 0x5a);
90 dsi_dphy_write(dsi, 0x20, (0x0));
91 dsi_dphy_write(dsi, 0x21, 0x28);
92 dsi_dphy_write(dsi, 0x22, 0xc);
93 dsi_dphy_write(dsi, 0x23, 0x9);
94 dsi_dphy_write(dsi, 0x24, 0x1a);
95 dsi_dphy_write(dsi, 0x25, 0xa);
96
97 for (i = 0; i < DS_NUM_LANES; i++) {
98 tmp = 0x30 + (i << 4);
99 dsi_dphy_write(dsi, tmp, 0x3c);
100 tmp = 0x31 + (i << 4);
101 dsi_dphy_write(dsi, tmp, 0x0);
102 dsi_dphy_write(dsi, tmp, 0xc);
103 tmp = 0x33 + (i << 4);
104 dsi_dphy_write(dsi, tmp, 0x8);
105 tmp = 0x34 + (i << 4);
106 dsi_dphy_write(dsi, tmp, 0xb);
107 tmp = 0x35 + (i << 4);
108 dsi_dphy_write(dsi, tmp, 0xb);
109 tmp = 0x36 + (i << 4);
110 dsi_dphy_write(dsi, tmp, 0x3);
111 tmp = 0x37 + (i << 4);
112 dsi_dphy_write(dsi, tmp, 0x4);
113 }
114 }
115
hdmi_gpio_init(dsi_t * dsi)116 static void hdmi_gpio_init(dsi_t* dsi) {
117 gpio_protocol_t* gpios = dsi->hdmi_gpio.gpios;
118 gpio_config_out(&gpios[GPIO_MUX], 0);
119 gpio_config_out(&gpios[GPIO_PD], 0);
120 gpio_config_in(&gpios[GPIO_INT], GPIO_NO_PULL);
121 gpio_write(&gpios[GPIO_MUX], 0);
122 }
123
dsi_release(void * ctx)124 static void dsi_release(void* ctx) {
125 dsi_t* dsi = ctx;
126 mmio_buffer_release(&dsi->mmio);
127 free(dsi);
128 }
129
dsi_get_protocol(void * ctx,uint32_t proto_id,void * out)130 static zx_status_t dsi_get_protocol(void* ctx, uint32_t proto_id, void* out) {
131 return ZX_OK;
132 }
133
134 static zx_protocol_device_t dsi_device_proto = {
135 .version = DEVICE_OPS_VERSION,
136 .get_protocol = dsi_get_protocol,
137 .release = dsi_release,
138 };
139
dsi_mipi_test(dsi_t * dsi)140 static zx_status_t dsi_mipi_test(dsi_t* dsi) {
141
142 // enable video mode
143 DW_DSI_SET_BITS32(DW_DSI_MODE_CFG, 0x0, 1, 0);
144
145 // configure dpi color coding
146 DW_DSI_SET_BITS32(DW_DSI_DPI_COLOR_CODING, 0x5, 4, 0);
147
148 DW_DSI_SET_BITS32(DW_DSI_VID_MODE_CFG, 1, 1, 16);
149
150 return ZX_OK;
151 }
152
dsi_configure_dphy(dsi_t * dsi)153 static zx_status_t dsi_configure_dphy(dsi_t* dsi) {
154 uint32_t tmp = 0;
155
156 // D-PHY shutdown and reset
157 DW_DSI_WRITE32(DW_DSI_PHY_RSTZ, DW_DSI_PHY_RSTZ_SHUTDOWN);
158
159 // Configure number of lanes
160 DW_DSI_SET_BITS32(DW_DSI_PHY_IF_CFG, (DS_NUM_LANES - 1), 2, 0);
161
162 // Configure TX_EST to frequency lower than 20MHz. Since byte clock is limited to 187.5MHz,
163 // write 0x09 will always generate clock less than 20MHz
164 DW_DSI_SET_BITS32(DW_DSI_CLKMGR_CFG, 0x09, 8, 0);
165
166 // Configure PHY PLL values
167 dsi_configure_dphy_pll(dsi);
168
169 // Enable PHY
170 DW_DSI_WRITE32(DW_DSI_PHY_RSTZ, DW_DSI_PHY_RSTZ_ENABLE);
171
172 // Wait for it to complete
173 // TODO: Define some sort of timeout
174 tmp = DW_DSI_READ32(DW_DSI_PHY_STATUS);
175 while ((tmp & DW_DSI_PHY_STATUS_PHY_LOCKED) != DW_DSI_PHY_STATUS_PHY_LOCKED) {
176 usleep(1000);
177 tmp = DW_DSI_READ32(DW_DSI_PHY_STATUS);
178 }
179
180 /* Wait for all four lan*/
181 // TODO: Define some sort of timeout
182 tmp = DW_DSI_READ32(DW_DSI_PHY_STATUS);
183 while ((tmp & DW_DSI_PHY_STATUS_ALLSTOP) != DW_DSI_PHY_STATUS_ALLSTOP) {
184 usleep(1000);
185 tmp = DW_DSI_READ32(DW_DSI_PHY_STATUS);
186 }
187
188 return ZX_OK;
189 }
190
dsi_configure_dpi_interface(dsi_t * dsi)191 static void dsi_configure_dpi_interface(dsi_t* dsi) {
192 // Configure the virtual channel of the generated packets (0 since single display mode)
193 DW_DSI_SET_BITS32(DW_DSI_DPI_VCID, 0x0, 2, 0);
194
195 // Configure bpp (bits per pixel). Set to 24 bit
196 DW_DSI_SET_BITS32(DW_DSI_DPI_COLOR_CODING, DSI_COLOR_CODE_24BITS, 4, 0);
197
198 // Configure the polarity of dpidataen (active high)
199 DW_DSI_SET_BITS32(DW_DSI_DPI_CFG_POL, DSI_CFG_POL_ACTIVE_HIGH, 1,
200 DW_DSI_DPI_CFG_POL_DATAEN_START);
201
202 // Configure the polarity of vsync (active high)
203 DW_DSI_SET_BITS32(DW_DSI_DPI_CFG_POL, DSI_CFG_POL_ACTIVE_HIGH, 1,
204 DW_DSI_DPI_CFG_POL_VSYNC_START);
205
206 // Configure the polarity of hsync (active high)
207 DW_DSI_SET_BITS32(DW_DSI_DPI_CFG_POL, DSI_CFG_POL_ACTIVE_HIGH, 1,
208 DW_DSI_DPI_CFG_POL_HSYNC_START);
209
210 // Configure the polarity of shutd (active high)
211 DW_DSI_SET_BITS32(DW_DSI_DPI_CFG_POL, DSI_CFG_POL_ACTIVE_HIGH, 1,
212 DW_DSI_DPI_CFG_POL_SHUTD_START);
213
214 // Configure the polarity of colorm (active high)
215 DW_DSI_SET_BITS32(DW_DSI_DPI_CFG_POL, DSI_CFG_POL_ACTIVE_HIGH, 1,
216 DW_DSI_DPI_CFG_POL_COLORM_START);
217
218 }
219
dsi_mipi_init(dsi_t * dsi)220 static zx_status_t dsi_mipi_init(dsi_t* dsi) {
221 uint64_t pixel_clk = 0;
222 uint32_t hdisplay;
223 uint32_t vdisplay;
224 uint32_t hsync_start;
225 uint32_t hsync_end;
226 uint32_t htotal;
227 uint32_t vsync_start;
228 uint32_t vsync_end;
229 uint32_t vtotal;
230 uint32_t hfp;
231 uint32_t hbp;
232 uint32_t vfp;
233 uint32_t vbp;
234 uint32_t hpw;
235 uint32_t vpw;
236 uint32_t hsa_time;
237 uint32_t hbp_time;
238 uint32_t hline_time;
239
240 /* Below values are calculated based on PHY parameters which we don't know */
241 uint32_t clk_lane_lp2hs_time = 0x3f;
242 uint32_t clk_lane_hs2lp_time = 0x3a;
243 uint32_t data_lane_lp2hs_time = 0x68;
244 uint32_t data_lane_hs2lp_time = 0x13;
245
246 // reset core
247 DW_DSI_WRITE32(DW_DSI_PWR_UP, 0);
248
249 // Configure DPHY
250 dsi_configure_dphy(dsi);
251
252 /* MIPI-DSI Spec Section 3.1.1 */
253 dsi_configure_dpi_interface(dsi);
254
255 // Configure low-power transitions whenever possible
256 DW_DSI_SET_BITS32(DW_DSI_VID_MODE_CFG, DW_DSI_VID_MODE_CFG_ALL_LP,
257 DW_DSI_VID_MODE_CFG_LP_ALL_BITS, DW_DSI_VID_MODE_CFG_LP_ALL_START);
258
259 // Configure whether controller should request ack msg at end of frame (no need)
260 DW_DSI_SET_BITS32(DW_DSI_VID_MODE_CFG, 0x0, DW_DSI_VID_MODE_CFG_FRAME_ACK_BITS,
261 DW_DSI_VID_MODE_CFG_FRAME_ACK_START);
262
263 // Configure commands to be sent in low power mode only
264 DW_DSI_SET_BITS32(DW_DSI_VID_MODE_CFG, 0x1, DW_DSI_VID_MODE_CFG_LP_CMD_BITS,
265 DW_DSI_VID_MODE_CFG_LP_CMD_START);
266
267 // set mode to Non-burst with sync pulses
268 DW_DSI_SET_BITS32(DW_DSI_VID_MODE_CFG, DSI_NON_BURST_SYNC_PULSES,
269 DW_DSI_VID_MODE_CFG_MODE_BITS, DW_DSI_VID_MODE_CFG_MODE_START);
270
271 // Set number of pixel in a single video packet
272 DW_DSI_SET_BITS32(DW_DSI_VID_PKT_SIZE, dsi->std_disp_timing->HActive,
273 DW_DSI_VID_PKT_SIZE_BITS, DW_DSI_VID_PKT_SIZE_START);
274
275 // Configure number of packets to be transmitted per video line (0 for single transmission)
276 DW_DSI_WRITE32(DW_DSI_VID_NUM_CHUNKS, 0);
277
278 // Disable null packet
279 DW_DSI_WRITE32(DW_DSI_VID_NULL_SIZE, 0);
280
281 /* TODO: fix blank display bug when set backlight*/
282 DW_DSI_SET_BITS32(DW_DSI_DPI_LP_CMD_TIM, 0x4, 8, 16);
283
284 /* for dsi read, BTA enable*/
285 DW_DSI_SET_BITS32(DW_DSI_PCKHDL_CFG, 0x1, 1, 2);
286
287 // Define DPI Horizontal and Vertical timing configuration
288
289
290 // TODO: This is a hardcoded value in the Android source.
291 // Supposed to be: pixel_clk = dsi->std_disp_timing->pixel_clk * 10000;
292 pixel_clk = 144000000;
293 hdisplay = dsi->std_disp_timing->HActive;
294 vdisplay = dsi->std_disp_timing->VActive;
295 hsync_start = dsi->std_disp_timing->HActive + dsi->std_disp_timing->HSyncOffset;
296 vsync_start = dsi->std_disp_timing->VActive + dsi->std_disp_timing->VSyncOffset;
297 hsync_end = hsync_start + dsi->std_disp_timing->HSyncPulseWidth;
298 vsync_end = vsync_start + dsi->std_disp_timing->VSyncPulseWidth;
299 htotal = dsi->std_disp_timing->HActive + dsi->std_disp_timing->HBlanking;
300 vtotal = dsi->std_disp_timing->VActive + dsi->std_disp_timing->VBlanking;
301
302 hfp = hsync_start - hdisplay;
303 hbp = htotal - hsync_end;
304 hpw = hsync_end - hsync_start;
305 vfp = vsync_start - vdisplay;
306 vbp = vtotal - vsync_end;
307 vpw = vsync_end - vsync_start;
308
309 hsa_time = (hpw * LANE_BYTE_CLOCK) / pixel_clk;
310 hbp_time = (hbp * LANE_BYTE_CLOCK) / pixel_clk;
311 hline_time = ROUND1((hpw + hbp + hfp + hdisplay) * LANE_BYTE_CLOCK, pixel_clk);
312
313 DW_DSI_SET_BITS32(DW_DSI_VID_HSA_TIME, hsa_time, 12, 0);
314 DW_DSI_SET_BITS32(DW_DSI_VID_HBP_TIME, hbp_time, 12, 0);
315 DW_DSI_SET_BITS32(DW_DSI_VID_HLINE_TIME, hline_time, 15, 0);
316
317 /* Define the Vertical line configuration*/
318 DW_DSI_SET_BITS32(DW_DSI_VID_VSA_LINES, vpw, 10, 0);
319 DW_DSI_SET_BITS32(DW_DSI_VID_VBP_LINES, vbp, 10, 0);
320 DW_DSI_SET_BITS32(DW_DSI_VID_VFP_LINES, vfp, 10, 0);
321 DW_DSI_SET_BITS32(DW_DSI_VID_VACTIVE_LINES, vdisplay, 14, 0);
322 DW_DSI_SET_BITS32(DW_DSI_TO_CNT_CFG, 0x7FF, 16, 0);
323
324 /* Configure core's phy parameters*/
325 DW_DSI_SET_BITS32(DW_DSI_PHY_TMR_LPCLK_CFG, clk_lane_lp2hs_time, 10, 0);
326 DW_DSI_SET_BITS32(DW_DSI_PHY_TMR_LPCLK_CFG, clk_lane_hs2lp_time, 10, 16);
327
328 DW_DSI_SET_BITS32(DW_DSI_PHY_TMR_RD_CFG, 0x7FFF, 15, 0);
329 DW_DSI_SET_BITS32(DW_DSI_PHY_TMR_CFG, data_lane_lp2hs_time, 10, 0);
330 DW_DSI_SET_BITS32(DW_DSI_PHY_TMR_CFG, data_lane_hs2lp_time, 10, 16);
331
332 /* Waking up Core*/
333 DW_DSI_SET_BITS32(DW_DSI_PWR_UP, 0x1, 1, 0);
334
335 /* Make sure we are in video mode */
336 DW_DSI_SET_BITS32(DW_DSI_MODE_CFG, 0x0, 1, 0);
337
338 /* Enable EoTp Transmission */
339 DW_DSI_SET_BITS32(DW_DSI_PCKHDL_CFG, 0x1, 1, 0);
340
341 /* Generate High Speed clock, Continuous clock */
342 DW_DSI_SET_BITS32(DW_DSI_LPCLK_CTRL, 0x1, 2, 0);
343
344 return ZX_OK;
345 }
346
dsi_bind(void * ctx,zx_device_t * parent)347 static zx_status_t dsi_bind(void* ctx, zx_device_t* parent) {
348 zxlogf(INFO, "dsi_bind\n");
349
350 dsi_t* dsi = calloc(1, sizeof(dsi_t));
351 if (!dsi) {
352 return ZX_ERR_NO_MEMORY;
353 }
354
355 zx_status_t status = device_get_protocol(parent, ZX_PROTOCOL_PDEV, &dsi->pdev);
356 if (status != ZX_OK) {
357 goto fail;
358 }
359 dsi->parent = parent;
360
361 status = pdev_map_mmio_buffer2(&dsi->pdev, 0, ZX_CACHE_POLICY_UNCACHED_DEVICE,
362 &dsi->mmio);
363 if (status != ZX_OK) {
364 zxlogf(ERROR, "dsi_bind: pdev_map_mmio_buffer failed\n");
365 goto fail;
366 }
367
368 /* Obtain the I2C devices */
369 size_t actual;
370 if (pdev_get_protocol(&dsi->pdev, ZX_PROTOCOL_I2C, 0, &dsi->i2c_dev.i2c_main,
371 sizeof(dsi->i2c_dev.i2c_main), &actual) != ZX_OK) {
372 zxlogf(ERROR, "%s: Could not obtain I2C Protocol\n", __FUNCTION__);
373 goto fail;
374 }
375 if (pdev_get_protocol(&dsi->pdev, ZX_PROTOCOL_I2C, 1, &dsi->i2c_dev.i2c_cec,
376 sizeof(dsi->i2c_dev.i2c_cec), &actual) != ZX_OK) {
377 zxlogf(ERROR, "%s: Could not obtain I2C Protocol\n", __FUNCTION__);
378 goto fail;
379 }
380 if (pdev_get_protocol(&dsi->pdev, ZX_PROTOCOL_I2C, 2, &dsi->i2c_dev.i2c_edid,
381 sizeof(dsi->i2c_dev.i2c_edid), &actual) != ZX_OK) {
382 zxlogf(ERROR, "%s: Could not obtain I2C Protocol\n", __FUNCTION__);
383 goto fail;
384 }
385
386 /* Obtain the GPIO devices */
387 for (uint32_t i = 0; i < countof(dsi->hdmi_gpio.gpios); i++) {
388 if (pdev_get_protocol(&dsi->pdev, ZX_PROTOCOL_GPIO, i, &dsi->hdmi_gpio.gpios[i],
389 sizeof(dsi->hdmi_gpio.gpios[i]), &actual) != ZX_OK) {
390 zxlogf(ERROR, "%s: Could not obtain GPIO Protocol\n", __FUNCTION__);
391 goto fail;
392 }
393 }
394
395 hdmi_gpio_init(dsi);
396
397 if ( (status = adv7533_init(dsi)) != ZX_OK) {
398 zxlogf(ERROR, "%s: Error in ADV7533 Initialization %d\n", __FUNCTION__, status);
399 goto fail;
400 }
401 dsi_get_display_timing(dsi);
402 dsi_mipi_init(dsi);
403 hdmi_init(dsi);
404 dsi_mipi_test(dsi);
405
406 // dsi_mipi_init(dsi);
407 zxlogf(INFO, "MIPI Initialized. Version is 0x%x\n", readl(dsi->mmio.vaddr));
408
409 device_add_args_t args = {
410 .version = DEVICE_ADD_ARGS_VERSION,
411 .name = "dsi",
412 .ctx = dsi,
413 .ops = &dsi_device_proto,
414 .proto_id = 0,
415 .proto_ops = 0,
416 };
417
418 status = device_add(parent, &args, &dsi->zxdev);
419 if (status != ZX_OK) {
420 goto fail;
421 }
422
423 return ZX_OK;
424
425 fail:
426 zxlogf(ERROR, "dsi3_bind failed %d\n", status);
427 dsi_release(dsi);
428 return status;
429
430 }
431
432 static zx_driver_ops_t dsi_driver_ops = {
433 .version = DRIVER_OPS_VERSION,
434 .bind = dsi_bind,
435 };
436
437 // The formatter does not play nice with these macros.
438 // clang-format off
439 ZIRCON_DRIVER_BEGIN(dsi, dsi_driver_ops, "zircon", "0.1", 3)
440 BI_ABORT_IF(NE, BIND_PLATFORM_DEV_VID, PDEV_VID_GENERIC),
441 BI_ABORT_IF(NE, BIND_PLATFORM_DEV_PID, PDEV_PID_GENERIC),
442 BI_MATCH_IF(EQ, BIND_PLATFORM_DEV_DID, PDEV_DID_DSI),
443 ZIRCON_DRIVER_END(dsi)
444 // clang-format on
445