1 // Copyright 2018 The Fuchsia Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #pragma once
6 
7 __BEGIN_CDECLS
8 
9 // clang-format off
10 
11 //PDM control registers
12 #define PDM_CTRL                    (0x00 << 2)
13 #define PDM_HCIC_CTRL1              (0x01 << 2)
14 #define PDM_HCIC_CTRL2              (0x02 << 2)
15 #define PDM_F1_CTRL                 (0x03 << 2)
16 #define PDM_F2_CTRL                 (0x04 << 2)
17 #define PDM_F3_CTRL                 (0x05 << 2)
18 #define PDM_HPF_CTRL                (0x06 << 2)
19 #define PDM_CHAN_CTRL               (0x07 << 2)
20 #define PDM_CHAN_CTRL1              (0x08 << 2)
21 #define PDM_COEFF_ADDR              (0x09 << 2)
22 #define PDM_COEFF_DATA              (0x0a << 2)
23 #define PDM_CLKG_CTRL               (0x0b << 2)
24 #define PDM_STS                     (0x0c << 2)
25 
26 
27 //Clock control registers
28 #define EE_AUDIO_MCLK_ENA            (1 << 31)
29 
30 #define EE_AUDIO_CLK_GATE_EN        0x0000
31 #define EE_AUDIO_MCLK_A_CTRL        0x0004
32 #define EE_AUDIO_MCLK_B_CTRL        0x0008
33 #define EE_AUDIO_MCLK_C_CTRL        0x000C
34 #define EE_AUDIO_MCLK_D_CTRL        0x0010
35 #define EE_AUDIO_MCLK_E_CTRL        0x0014
36 #define EE_AUDIO_MCLK_F_CTRL        0x0018
37 
38 #define EE_AUDIO_MST_PAD_CTRL0      0x001C
39 #define EE_AUDIO_MST_PAD_CTRL1      0x0020
40 
41 #define EE_AUDIO_MST_A_SCLK_CTRL0     0x0040
42 #define EE_AUDIO_MST_A_SCLK_CTRL1     0x0044
43 #define EE_AUDIO_MST_B_SCLK_CTRL0     0x0048
44 #define EE_AUDIO_MST_B_SCLK_CTRL1     0x004C
45 #define EE_AUDIO_MST_C_SCLK_CTRL0     0x0050
46 #define EE_AUDIO_MST_C_SCLK_CTRL1     0x0054
47 #define EE_AUDIO_MST_D_SCLK_CTRL0     0x0058
48 #define EE_AUDIO_MST_D_SCLK_CTRL1     0x005C
49 #define EE_AUDIO_MST_E_SCLK_CTRL0     0x0060
50 #define EE_AUDIO_MST_E_SCLK_CTRL1     0x0064
51 #define EE_AUDIO_MST_F_SCLK_CTRL0     0x0068
52 #define EE_AUDIO_MST_F_SCLK_CTRL1     0x006c
53 
54 #define EE_AUDIO_CLK_TDMOUT_A_CTL     0x0090
55 #define EE_AUDIO_CLK_TDMOUT_B_CTL     0x0094
56 #define EE_AUDIO_CLK_TDMOUT_C_CTL     0x0098
57 
58 #define EE_AUDIO_CLK_PDMIN_CTRL0      0x00ac
59 #define EE_AUDIO_CLK_PDMIN_CTRL1      0x00b0
60 
61 //TODDR control reg blocks and offsets
62 #define TODDR_CTRL0_OFFS        (0x00)
63 #define TODDR_CTRL1_OFFS        (0x04)
64 #define TODDR_START_ADDR_OFFS   (0x08)
65 #define TODDR_FINISH_ADDR_OFFS  (0x0c)
66 #define TODDR_INT_ADDR_OFFS     (0x10)
67 #define TODDR_STATUS1_OFFS      (0x14)
68 #define TODDR_STATUS2_OFFS      (0x18)
69 #define TODDR_START_ADDRB_OFFS  (0x1c)
70 #define TODDR_FINISH_ADDRB_OFFS (0x20)
71 #define TODDR_INIT_ADDR_OFFS    (0x24)
72 
73 
74 //FRDDR control reg blocks and offsets
75 #define FRDDR_CTRL0_OFFS        (0x00)
76 #define FRDDR_CTRL1_OFFS        (0x04)
77 #define FRDDR_START_ADDR_OFFS   (0x08)
78 #define FRDDR_FINISH_ADDR_OFFS  (0x0c)
79 #define FRDDR_INT_ADDR_OFFS     (0x10)
80 #define FRDDR_STATUS1_OFFS      (0x14)
81 #define FRDDR_STATUS2_OFFS      (0x18)
82 
83 #define EE_AUDIO_TODDR_A_CTRL0       (0x40 << 2)
84 #define EE_AUDIO_TODDR_B_CTRL0       (0x50 << 2)
85 #define EE_AUDIO_TODDR_C_CTRL0       (0x60 << 2)
86 #define EE_AUDIO_FRDDR_A_CTRL0       (0x70 << 2)
87 #define EE_AUDIO_FRDDR_B_CTRL0       (0x80 << 2)
88 #define EE_AUDIO_FRDDR_C_CTRL0       (0x90 << 2)
89 
90 #define EE_AUDIO_ARB_CTRL             (0xa0 << 2)
91 
92 //TDMOUT control regs (common to three separate units)
93 #define TDMOUT_CTRL0_OFFS     (0x00)
94 #define TDMOUT_CTRL1_OFFS     (0x04)
95 #define TDMOUT_SWAP_OFFS      (0x08)
96 #define TDMOUT_MASK0_OFFS     (0x0c)
97 #define TDMOUT_MASK1_OFFS     (0x10)
98 #define TDMOUT_MASK2_OFFS     (0x14)
99 #define TDMOUT_MASK3_OFFS     (0x18)
100 #define TDMOUT_STAT_OFFS      (0x1c)
101 #define TDMOUT_GAIN0_OFFS     (0x20)
102 #define TDMOUT_GAIN1_OFFS     (0x24)
103 #define TDMOUT_MUTE_VAL_OFFS  (0x28)
104 #define TDMOUT_MUTE0_OFFS     (0x2c)
105 #define TDMOUT_MUTE1_OFFS     (0x30)
106 #define TDMOUT_MUTE2_OFFS     (0x34)
107 #define TDMOUT_MUTE3_OFFS     (0x38)
108 #define TDMOUT_MASK_VAL_OFFS  (0x3c)
109 
110 #define EE_AUDIO_TDMOUT_A_CTRL0         (0x140 << 2)
111 #define EE_AUDIO_TDMOUT_B_CTRL0         (0x150 << 2)
112 #define EE_AUDIO_TDMOUT_C_CTRL0         (0x160 << 2)
113 
114 
115 //Audio clock gating masks
116 #define EE_AUDIO_CLK_GATE_ARB        (1 << 0)
117 #define EE_AUDIO_CLK_GATE_PDM        (1 << 1)
118 #define EE_AUDIO_CLK_GATE_TDMINA     (1 << 2)
119 #define EE_AUDIO_CLK_GATE_TDMINB     (1 << 3)
120 #define EE_AUDIO_CLK_GATE_TDMINC     (1 << 4)
121 #define EE_AUDIO_CLK_GATE_TDMOUTA    (1 << 6)
122 #define EE_AUDIO_CLK_GATE_TDMOUTB    (1 << 7)
123 #define EE_AUDIO_CLK_GATE_TDMOUTC    (1 << 8)
124 #define EE_AUDIO_CLK_GATE_FRDDRA     (1 << 9)
125 #define EE_AUDIO_CLK_GATE_FRDDRB     (1 << 10)
126 #define EE_AUDIO_CLK_GATE_FRDDRC     (1 << 11)
127 #define EE_AUDIO_CLK_GATE_TODDRA     (1 << 12)
128 #define EE_AUDIO_CLK_GATE_TODDRB     (1 << 13)
129 #define EE_AUDIO_CLK_GATE_TODDRC     (1 << 14)
130 
131 
132 
133 typedef enum {
134     MP0_PLL = 0,
135     MP1_PLL = 1,
136     MP2_PLL = 2,
137     MP3_PLL = 3,
138     HIFI_PLL = 4,
139     FCLK_DIV3 = 5,
140     FCLK_DIV4 = 6,
141     GP0_PLL = 7
142 } ee_audio_mclk_src_t;
143 
144 typedef enum {
145     MCLK_A = 0,
146     MCLK_B,
147     MCLK_C,
148     MCLK_D,
149     MCLK_E,
150     MCLK_F
151 } aml_tdm_mclk_t;
152 
153 typedef enum {
154     MCLK_PAD_0 = 0,
155     MCLK_PAD_1
156 } aml_tdm_mclk_pad_t;
157 
158 typedef enum {
159     TDM_OUT_A = 0,
160     TDM_OUT_B,
161     TDM_OUT_C
162 } aml_tdm_out_t;
163 
164 typedef enum {
165     FRDDR_A = 0,
166     FRDDR_B,
167     FRDDR_C
168 } aml_frddr_t;
169 
170 typedef enum {
171     TODDR_A = 0,
172     TODDR_B,
173     TODDR_C
174 } aml_toddr_t;
175 
176 // clang-format on
177 __END_CDECLS
178