1 // Copyright 2018 The Fuchsia Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE 4 5 #pragma once 6 7 #include <hwreg/bitfields.h> 8 #include <hwreg/mmio.h> 9 #include <hw/reg.h> 10 11 namespace pcie { 12 namespace designware { 13 14 namespace PortLogic { 15 constexpr uint32_t Base = 0x700; 16 constexpr uint32_t DebugR1Offset = Base + 0x2c; 17 class DebugR1 : public hwreg::RegisterBase<DebugR1, uint32_t> { 18 public: 19 DEF_BIT(4, link_up); 20 DEF_BIT(29, link_in_training); Get()21 static auto Get() {return hwreg::RegisterAddr<DebugR1>(DebugR1Offset); } 22 }; 23 24 } // namespace PortLogic 25 26 #define PORT_LINK_CTRL_OFF (0x710) 27 #define PLC_VENDOR_SPECIFIC_DLLP_REQ (1 << 0) 28 #define PLC_SCRAMBLE_DISABLE (1 << 1) 29 #define PLC_LOOPBACK_ENABLE (1 << 2) 30 #define PLC_RESET_ASSERT (1 << 3) 31 #define PLC_DLL_LINK_EN (1 << 5) 32 #define PLC_LINK_DISABLE (1 << 6) 33 #define PLC_FAST_LINK_MODE (1 << 7) 34 #define PLC_LINK_RATE_MASK (0xF << 8) 35 #define PLC_LINK_CAPABLE_MASK (0x3F << 16) 36 #define PLC_LINK_CAPABLE_X1 (0x01 << 16) 37 #define PLC_LINK_CAPABLE_X2 (0x03 << 16) 38 #define PLC_LINK_CAPABLE_X4 (0x07 << 16) 39 #define PLC_LINK_CAPABLE_X8 (0x0f << 16) 40 #define PLC_LINK_CAPABLE_X16 (0x1f << 16) 41 #define PLC_BEACON_ENABLE (1 << 24) 42 #define PLC_CORRUPT_LCRC_ENABLE (1 << 25) 43 #define PLC_EXTENDED_SYNC_H (1 << 26) 44 #define PLC_TRANSMIT_LANE_REVERSAL_ENABLE (1 << 27) 45 46 #define GEN2_CTRL_OFF (0x80C) 47 #define G2_CTRL_FAST_TRAINING_SEQ_MASK (0xFF << 0) 48 #define G2_CTRL_NUM_OF_LANES_MASK (0x1F << 8) 49 #define G2_CTRL_NO_OF_LANES(x) ((x) << 8) 50 #define G2_CTRL_PRE_DET_LANE_MASK (0x07 << 13) 51 #define G2_CTRL_AUTO_LANE_FLIP_CTRL_EN (1 << 16) 52 #define G2_CTRL_DIRECT_SPEED_CHANGE (1 << 17) 53 #define G2_CTRL_CONFIG_PHY_TX_CHANGE (1 << 18) 54 #define G2_CTRL_CONFIG_TX_COMP_RX (1 << 19) 55 #define G2_CTRL_SEL_DEEMPHASIS (1 << 20) 56 #define G2_CTRL_GEN1_EI_INFERENCE (1 << 21) 57 58 #define PCIE_TLP_TYPE_MEM_RW (0x00) 59 #define PCIE_TLP_TYPE_MEM_RD_LOCKED (0x01) 60 #define PCIE_TLP_TYPE_IO_RW (0x02) 61 #define PCIE_TLP_TYPE_CFG0 (0x04) 62 #define PCIE_TLP_TYPE_CFG1 (0x05) 63 #define PCIE_ECAM_SIZE (0x1000) 64 65 #define PCI_TYPE1_BAR0 (0x10) 66 #define PCI_TYPE1_BAR1 (0x14) 67 68 const uint32_t kAtuRegionCount = (16); 69 const uint32_t kAtuRegionCtrlEnable = (1 << 31); 70 const uint32_t kAtuCfgShiftMode = (1 << 28); 71 const uint32_t kAtuProgramRetries = (5); 72 const uint32_t kAtuWaitEnableTimeoutUs = (10000); 73 74 typedef struct atu_ctrl_regs { 75 uint32_t region_ctrl1; 76 uint32_t region_ctrl2; 77 uint32_t unroll_lower_base; 78 uint32_t unroll_upper_base; 79 uint32_t unroll_limit; 80 uint32_t unroll_lower_target; 81 uint32_t unroll_upper_target; 82 } __PACKED atu_ctrl_regs_t; 83 84 } // namespace designware 85 86 } // namespace pcie 87